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boundary scan (jtag) does not find xilinx fpga
i cant get the boundary scan to detect my devices. i have a homemade board with a xilinx spartan 3e (xc3s100e) and a xilinx prom attached (xcf01svog20). the jtag device i use is a digilent xup usb-jtag programming cable. the scan only finds one devi...
PLD, SPLD, GAL, CPLD, FPGA Design :: 17 Nov 2009 17:10 :: schouten_tjeerd :: Replies: 4 :: Views: 102
wrapper file - pc to fpga communiction through pci
nd data from a pc via pci to the fpga, where the data will be processed (videoprocessing-algorithm), and then sent the result to the pc via pci.i already generated the vhdl-code of the algorithm with xilinx system generator and also have the vhdl-cod...
PLD, SPLD, GAL, CPLD, FPGA Design :: 17 Nov 2009 15:27 :: Ghostboy :: Replies: 1 :: Views: 111
mobile communication project on matlab
hi every1 ive just finished cdma project on fpga boards the design is from a-to-z digital even the summation process if any1 interested i can give a hand...,...
Digital communication :: 16 Nov 2009 17:53 :: rahul bakshi :: Replies: 68 :: Views: 8839
video and image processing in fpga
hi everyone...am tarun doin my final year b tech in telecommunication in vellore tamil nadu indiamy project title is driver alertness and alcohol detection using fpgai hv written the code for eye detection in matlab... i need to implement the algorit...
PLD, SPLD, GAL, CPLD, FPGA Design :: 15 Nov 2009 1:06 :: luya :: Replies: 32 :: Views: 4566
dds help
anyone please help . tell me the step to come out with dds 120 mhz 8 bit please help...
PLD, SPLD, GAL, CPLD, FPGA Design :: 12 Nov 2009 21:25 :: senior :: Replies: 30 :: Views: 1894
mig, ddr2 and virtex5 - tutorial or ise example
hi,can someone who has used xilinxs mig ddr2 controller help?i am trying to generate and simulate the ddr2 controller with memorymt47h16m16 memory model generated by mig 2.0 (xilinx ise 10.1> sp3)if someone has a tutorial or ise example.thanks in adv...
PLD, SPLD, GAL, CPLD, FPGA Design :: 12 Nov 2009 13:54 :: farhada :: Replies: 3 :: Views: 141
alrium vs xilinx ' .. xilinx ise not supported'
hi! im trying to program cpld in altium. its recognise my cpld thruout jtag. but it writes a message .. xilinx ise not supportedwhat is the problem?is here anybody?help me please?thanks!ficko...
PLD, SPLD, GAL, CPLD, FPGA Design :: 11 Nov 2009 21:53 :: ficko :: Replies: 6 :: Views: 654
cdma:simulation and implementation
i m the student of engineering final year.i m doing this project as my final year project.but implementation of cdma on fpga is completely new to me as i have no knowledge abt fpga.could anyone help me out with it and send me the entire details abt t...
Digital communication :: 10 Nov 2009 9:25 :: ahmad ammar asghar :: Replies: 2 :: Views: 174
altera and xilinx cables co-shareable?
do you know if i can use xilinx usb download http://www.xilinx.com/products/devkits/hw-usb-ii-g.htm cable with altera devices (arria gx fpga)? or do i need usb byteblaster http://www.buyaltera.com/scripts/partsearch.dll?detail&name=544-1775-ndof cour...
PLD, SPLD, GAL, CPLD, FPGA Design :: 09 Nov 2009 21:26 :: FvM :: Replies: 1 :: Views: 99
which vhdl/verilog editor is the best ?
which vhdl/verilog editor is the best ?features for categorizing:syntax highlighting,autoindentation,folding......
PLD, SPLD, GAL, CPLD, FPGA Design :: 06 Nov 2009 22:04 :: heeckhau :: Replies: 25 :: Views: 8088
handwritten recognition realization using fpga
hi all,i am an electrical engineering student doing final year project on handwritten recognition. i am thinking of using wavelet transform for feature extraction and hybrid of fuzzy logic with neural network for recognition. may i know any comments ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 06 Nov 2009 4:21 :: sengsengooi :: Replies: 5 :: Views: 303
implementation of video transmission module on fpga
this thread is for the embedded system engineers who are working on the implementation of video transmission module on fpga. i welcome you all. regards,p v s added after 59 minutes: i made use of the following software and hardware tools to impleme...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05 Nov 2009 13:20 :: alessio.riccardi :: Replies: 6 :: Views: 720
xilinx fpga and custom ip
hello evry bdy i have just started working on microblaze processor ....now im planning to build custom ip (anything like a small sequential ckt or a state machine ) and connect it with microblaze ...on fpga .....i dnt know how to build custom ips for...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04 Nov 2009 18:55 :: saqaw :: Replies: 1 :: Views: 99
needhelp ofdm bestverilog\vhdlcode on xilnx v2pro2vp70
hello, need a best ofdm code to implement on xilinx v2pro xcv2v70.....may i know if somebody is workin on this project or has already done it .pls tell me about the ofdm design exploration coding efficient for mimo ,wimax on xilinx fpga v2pro and o...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04 Nov 2009 17:43 :: mahe46 :: Replies: 0 :: Views: 51
xilinx fpga implementation of des algorithm
hi every body,this is venkat, recently i successfully completed des algorithmm in vhdl. now i would like to implement it on the xilinx spartan 3e fpga kit. can any one help me how to assign input and output pins. regarding this project related mat...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04 Nov 2009 15:56 :: Aser :: Replies: 2 :: Views: 126
what happened to 2d dct core ?
has anyone used forward 2d dct ip cores in the new xilinx ise environemnt? in the old ise, dct was part of xilinx coregen. to use it in the design, you just selected it from the list and specify parameters to create the ip. seems like xilinx removed ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 29 Oct 2009 0:30 :: rakko :: Replies: 0 :: Views: 60
help needed in implementing cdma on xilinx spartan 3 fpga
hello all :im donig a project on implementing cdma over xilinx spartan 3 fpga using vhdl, so if any body have done a similar project or can help ill be very thankful.thanks all....
PLD, SPLD, GAL, CPLD, FPGA Design :: 28 Oct 2009 17:21 :: samii :: Replies: 0 :: Views: 51
implementation of cdma on fpga
hi everyone, i am a dire in need student of avionics engineering final semester and i have to do project of implementation of cdma/ofdma multiple access scheme on an fpga platform. plz plz i am in desperate need of help for completion of my be degree...
Digital communication :: 27 Oct 2009 20:30 :: medra :: Replies: 3 :: Views: 267
implement arm cores on a fpga chip?
hi everyone, i am a master student and this is my first post on thisforum. my research group is looking for a multicore embedded platformfor deploying an in-house developed computer vision algorithm. ivechecked some available development boards and n...
PLD, SPLD, GAL, CPLD, FPGA Design :: 27 Oct 2009 10:13 :: kel8157 :: Replies: 4 :: Views: 408
fpga implementation of acs block in soft decision viterbi
hi all, i want to implement soft decision viterbi decoder in fpga. i have already implemented hard-decision decoding and the design works fine in xilinx fpga. we have implemented high bit clear circuit for path metrics normalization to reduce the are...
PLD, SPLD, GAL, CPLD, FPGA Design :: 27 Oct 2009 7:43 :: sridar :: Replies: 0 :: Views: 60
ds-cdma chip on xilinx fpga...hlp me...
hi.guys.i m going my final year project on imple. cdma chip on fpga.m goal are...1.generating .m file in matab for multi-channel users(only binary data sequnce).2.now generating .m file for analog speech signal,too...3.now,change hadamard code sequnc...
PLD, SPLD, GAL, CPLD, FPGA Design :: 26 Oct 2009 18:09 :: rahul bakshi :: Replies: 5 :: Views: 636
newbie question (regarding simulation of bufgce module)
hi, i am trying to implement the clock gating technique using the global clock buffers (virtex 5 fpga). for a start i made a small test project just to get familiar with the funtionality of the bufgce, which is required to be instantiated in the code...
PLD, SPLD, GAL, CPLD, FPGA Design :: 26 Oct 2009 16:34 :: sajal1975 :: Replies: 1 :: Views: 78
how to implement image segmentation algorithm on fpga kit
hi ,i have an algorithm in matlab for image segmentation.my goal is to to implement it on fpga . could any body please tell me steps to implement image segmentation program on fpga.do i need to write the vhdl program to implement it on fpga or is t...
PLD, SPLD, GAL, CPLD, FPGA Design :: 25 Oct 2009 9:29 :: Slorn :: Replies: 1 :: Views: 141
16-qam design in xilinx system generator in simulink
hi friends!, i am involved with software defined radio project. hence i need to design the fpga with all possible modulation esp for students study purpose. now that i have seen many websites for a proper knowledge of how to design 16-qam or 32-qam, ...
Digital communication :: 24 Oct 2009 19:57 :: farhada :: Replies: 1 :: Views: 216
convert of floating point number to binary in vhdl
haii need to knw is it possible to convert a floating point number to binary representation and vice versa....im using xilinx ise 9.2i....plz help........
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Oct 2009 11:48 :: Aser :: Replies: 5 :: Views: 489
20ys senior design engineer (board, fpga, asic, system)
i everyone, from the end of oct. 2009 i will be out of contract and looking for work in the following fields:- complex board design from concept to schematic, layout and mass production- fpga design (xilinx, altera etc) in vhdl- asic prototyping and ...
EDA Jobs, Promotions, Advertising :: 21 Oct 2009 9:24 :: salma ali bakr :: Replies: 3 :: Views: 321
about picoblaze processor
hi, i am doing a project using fpga and i need to use picoblaze processor for this. the reference paper suggest that picoblaze is embeded on the kit. i would like to know what all fpgas have this feature also whether it is embeded in it or do i nee...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Oct 2009 4:54 :: aravind4all :: Replies: 1 :: Views: 141
synopsys & cadence tutorial
hi , im at the beginning os asic design.i would like to know if is there a tutorial on the net teaching how to start with vhdl code and end with chip layout using synopsys dc,modelsim and cadence ic.thanks a lot politicantep.s.i know(not very wel...
ASIC Design Methodologies & Tools (Digital) :: 19 Oct 2009 15:36 :: rohiteda :: Replies: 31 :: Views: 6321
unisimand simprim?
is it normal for xilinx to give errors and warnings when compiling unisim and simprim??...
PLD, SPLD, GAL, CPLD, FPGA Design :: 19 Oct 2009 14:42 :: lmtg :: Replies: 8 :: Views: 297
what's the max frequency xilinx fpga can run?
for virtex 2 or virtex pro?thanks!...
PLD, SPLD, GAL, CPLD, FPGA Design :: 16 Oct 2009 5:30 :: veejain :: Replies: 7 :: Views: 1069
can anybody help m to learn edk
i can able to do only vry vry simple application as glowing led and reading key....
PLD, SPLD, GAL, CPLD, FPGA Design :: 15 Oct 2009 9:55 :: xtcx :: Replies: 10 :: Views: 1056
help needed for parallel processing of modelsim simulation
i am working on fpga project, which simulation takes require time of one day, the constraint of time on simulation is making my progress slow on this project. in this regard can any one tell me how can i process my design simulation on parallel pcs, ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 13 Oct 2009 8:30 :: farhada :: Replies: 8 :: Views: 357
free 8051 ip core from oregano
hi there,ive found the free 8051 ip core from oregano, but unfortunately i have not found any sample project for this. im a beginner in fpga cores, so i need some help to implement this core in my project.you can find this core here:http://www.oregan...
PLD, SPLD, GAL, CPLD, FPGA Design :: 12 Oct 2009 14:09 :: bakabaka :: Replies: 16 :: Views: 2199
why use fpga's for oscilloscopes?
i posted this last night and i either posted in the wrong thread or it was moved. hobby circuits and small projects is where i wanted it so....lets try again.ive been scouring the web looking at different homebrew oscilloscope solutions and have foun...
Hobby Circuits and Small Projects Problems :: 12 Oct 2009 9:29 :: Mehdi1357 :: Replies: 5 :: Views: 432
fpga developer / designer (iptv) (oslo, norway)
fpga developerour client is expanding its product development team. we are looking for an enthusiasticand skilled fpga designer. the right person will be developing products and handlinglive tv distribution. fpga development works closely with the so...
EDA Jobs, Promotions, Advertising :: 11 Oct 2009 20:56 :: Samepoint :: Replies: 0 :: Views: 201
how can i build a fpga controller
hi all,1. how am i going to create a fpga controller to control another fpga board? 2. the fpga controller must be able to load the bit stream file from computer via ethernet interface and save it in the memory. next, the second fpga board will recei...
PLD, SPLD, GAL, CPLD, FPGA Design :: 11 Oct 2009 16:41 :: teesengwah :: Replies: 8 :: Views: 483
timing analyses using xilinx timing analyzer
hi experts, using xilinx timing analyzer shall we do the timing analysis of the combinational design.if it is possible how can we do.regards,kanimozhi.m...
PLD, SPLD, GAL, CPLD, FPGA Design :: 11 Oct 2009 12:04 :: sanjayk :: Replies: 3 :: Views: 186
how to configure spartan using 8051
i want to configure spartan using flash rom (29f010,..) and microcontroller 8051. can anybody help me?thanks...
PLD, SPLD, GAL, CPLD, FPGA Design :: 10 Oct 2009 19:27 :: BuBEE :: Replies: 7 :: Views: 836
spartan3 jtag interface 3.3v
hello, i had built the schematic on the application note xapp453, pg 8. i could program fpga, also prom, but when i did not have the jtag attached to the board, the prom was unable to download the bitcode to the fpga. now, i need to fix this issue ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 09 Oct 2009 12:32 :: System.out :: Replies: 0 :: Views: 132
ip cores
is there anyone out there who has worked with ip-core or zpu processor(from www.opencores.org) or any soft-core processor?? i need to implement a zpu processor in fpga cyclone.then i should make a simple programm for the zpu processor in order to sh...
PLD, SPLD, GAL, CPLD, FPGA Design :: 08 Oct 2009 23:18 :: kickbeer :: Replies: 5 :: Views: 648
good place to buy a used xilinx spartan development kit
can anybody recommend a good place to buy a used xilinx spartan development kit.tried craigslist and ebay - no luck.thanks...
Business Special Interest Group :: 07 Oct 2009 3:14 :: OutputLogic :: Replies: 2 :: Views: 318
anyone used opencore i2c mastercore successfully?
anyone used opencore i2c mastercore successfully?your help would be highly appreciated.thanx...
PLD, SPLD, GAL, CPLD, FPGA Design :: 06 Oct 2009 17:57 :: naz56 :: Replies: 13 :: Views: 420
fpga achitecture - request for resources
can any body refer some books about architecture of fpga...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05 Oct 2009 3:18 :: thuyet :: Replies: 1 :: Views: 183
fpga emulation - problem with cable connection
im havin xc 3s400 fpga kit with me. while im downloading the program to the kit , im getting a message like this. check the cable connection.plzz help me with needful...
PLD, SPLD, GAL, CPLD, FPGA Design :: 03 Oct 2009 14:14 :: menagarani :: Replies: 4 :: Views: 231
how to determine number of clock/global lines using xilinx?
hi all,can anyone share how to determine number of clock/global lines using xilinx ise software?i am looking at the pinout report. i saw there is some pin name named *gclk* and *chclk*. is this pin the clock/global lines?thanks....
PLD, SPLD, GAL, CPLD, FPGA Design :: 01 Oct 2009 2:41 :: palai_santosh :: Replies: 5 :: Views: 147
which fpga board fits this requirement?
higher spec than the digilent nexys 2-1200 in terms of fpga chip, has some sram/sdram and flash for data storage as well. some adc/dac and some text/number display, i also need high speed data interface which can connect to pc for data transfer and c...
PLD, SPLD, GAL, CPLD, FPGA Design :: 29 Sep 2009 15:41 :: kel8157 :: Replies: 2 :: Views: 222
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how to use fpga generate the digital sinwave code to dac?
hello,guys. now i need use fpga to generate the 12bit digital sinwave code (that mean the 12bit digital code restore to analog signal is a sinwavw)to control dac to test my dac snr and sndr, anyone can give me some suggestion how to generate this 12...
PLD, SPLD, GAL, CPLD, FPGA Design :: 29 Sep 2009 12:23 :: shitansh :: Replies: 4 :: Views: 210
spi vhdl code
please send me,spi vhdl code ,read data from spi and write to inside memory of fpga ic xilinx spartan 2...
PLD, SPLD, GAL, CPLD, FPGA Design :: 29 Sep 2009 9:50 :: farhada :: Replies: 1 :: Views: 369
may be some one make use of this topic
sampling---------------------------converting an analog signal to a digital one is a necessary step for a computer toanalyze a signal: modern computers are digital machines, and can store only digital values.in the continuous function x(t), we replac...
Digital Signal Processing :: 28 Sep 2009 18:57 :: Aya2002 :: Replies: 12 :: Views: 2225
project based on cpld or fpga?? help me
hello,i am new to this field. we have to interface keypad,lcd, and serially communicate with pc. our aim is to vary the output of programmable device in less than 1ms. we need to control 32 o/p. we have to design our own hardware. for our applica...
PLD, SPLD, GAL, CPLD, FPGA Design :: 28 Sep 2009 8:52 :: farhada :: Replies: 1 :: Views: 345
fpga missing in jtag chain
hi, i have developed a spartan ii board, and i have a problem configuring it. when impact tries to detect the devices on the jtag chain, which contains a prom and the fpga, the fpga is missing, and ofcourse all programming commands to the prom fail (...
PLD, SPLD, GAL, CPLD, FPGA Design :: 27 Sep 2009 19:55 :: farhada :: Replies: 1 :: Views: 195
about this speech recognition using fpga
i found this link of using speech recognition using neural network and fpga.http://www.courses.cit.cornell.edu/ece576/finalprojects/f2008/pae26_jsc59/pae26_jsc59/index.html .it provides the main code in c as below :my problems are how to find out the...
Digital Signal Processing :: 27 Sep 2009 18:42 :: farhada :: Replies: 1 :: Views: 252
how to simulate netlists such as edif and ngc files ?
hi , if we want to instantiate an edif or ngc netlist file in a vhdl code , then how can we simulate it in modelsim or activehdl ?in modelsim when i copy the edif file or ngc file in my folder , after i write a vhdl code and instantiate it as a compo...
PLD, SPLD, GAL, CPLD, FPGA Design :: 27 Sep 2009 13:35 :: farhada :: Replies: 3 :: Views: 234
help needed in hardware co-simulation
can anyone please help in guiding hardware co-simulation on xilinx ml505 vertex 5 board?????please ...!...
Digital Signal Processing :: 27 Sep 2009 13:26 :: farhada :: Replies: 4 :: Views: 195
video processing on fpga
hi all,ive to develop an application in which i should mux an itu656 input and i2s input, and output an hdmithe following component is very nice for what i should dohxxp://www.nxp.com/acrobat/datasheets/tda9989_2.pdfbut it costs a lot and i just need...
PLD, SPLD, GAL, CPLD, FPGA Design :: 22 Sep 2009 11:16 :: farhada :: Replies: 2 :: Views: 408
free high level synthesizers (systemc)
hi,is there any free high level synthesizer to convert systemc to vhdl or verilog or netlist or any sort of hardware description ?!thanks in advance,salma :)...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Sep 2009 16:05 :: C4Cheema :: Replies: 10 :: Views: 546
internal bus implemented inside fpga.
i read material says that bus can be implemented in fpga using multiplexer. is there anyone kindly enough to explain me how it works ? and are there any resources ,say,tri-state logic gates, inside fpga? or tri-state gates only available when using ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 21 Sep 2009 7:15 :: tkbits :: Replies: 10 :: Views: 1107
scenario - short on fpga pins
hi, this is a question from electrical behavior point of view. what will happen when 2 output pins of the fpga gets short and driving complementory logic? lets consider that the 2 pins are lvcmos. one driving logic high and the other logic low. is ...
PLD, SPLD, GAL, CPLD, FPGA Design :: 20 Sep 2009 4:38 :: farhada :: Replies: 1 :: Views: 240
h.264 decoder
hi,i am going to design a low power h.264 decoder.can anyone share any experience in video codec design or share me some information about h.264?thanks in advance!...
ASIC Design Methodologies & Tools (Digital) :: 19 Sep 2009 8:51 :: cihchenlin :: Replies: 36 :: Views: 5943
looking for sofware for rtl synthesis, preferably free ones
hello, i m looking for a software which can if not synthesis at least can analyze my rtl. give me the gate count and other details. please, suggest if there are any such free softwares ?? if i could do a little bit of sta with then ... the...
Software Requests :: 17 Sep 2009 14:26 :: andy2000akimo :: Replies: 1 :: Views: 366
need fpga development kit ....
dear all,if anybody want to sell used fpga development kit in india, please inform me. i am looking for one with xilinx device.regards,vamanan...
PLD, SPLD, GAL, CPLD, FPGA Design :: 17 Sep 2009 11:01 :: vamanan :: Replies: 5 :: Views: 423
camera interfacing to the fpga..
hi i m be elct. student.. i m planning to do project in vlsitheme is interfacing vga camera to fpgaso i m collecting information regarding how to connect camera to fpga n algorithm for same.. and how to wite code for same. which fpga board i should...
PLD, SPLD, GAL, CPLD, FPGA Design :: 15 Sep 2009 15:24 :: kkpowar :: Replies: 6 :: Views: 594
hdmi splitter by fpga (hdmi designer pls take a look)
i am now trying to make a hdmi 1-8 splitter with a xilinx spartan 3a. this fpga supports tmds i/o standard. i think it is no problem to split tmds channel and clock signals. however, i am getting puzzled to split other control signal listed below....
Professional Hardware and Electronics Design :: 14 Sep 2009 19:37 :: farhada :: Replies: 2 :: Views: 717
is xilinx infer arrays used in code to bram or dram?
hello,when arrays are used in code then xst maps it to where by default?? into block ram? or into distributed ram?a big confusion... difference between block ram and distributed ram?helpregards...
PLD, SPLD, GAL, CPLD, FPGA Design :: 14 Sep 2009 8:49 :: naz56 :: Replies: 4 :: Views: 222
help~~complexsignal in system generator
hallo all guys,im working with the xilinx sysgen and was building up a system for simulation. i have now a complexsignal and need to decompose this complexsignal into amplitude and phase.how can this be achieved in sysgen???thanks in advance...
PLD, SPLD, GAL, CPLD, FPGA Design :: 14 Sep 2009 1:51 :: palai_santosh :: Replies: 3 :: Views: 138
how to use block ram in spartan-3e?
bove question... may i know how to use block ram in spartan-3e?or any place i can find related information? (i cannot determine which keywords or which parts i shall search, googling and searching in xilinx webpage, most of the searched results menti...
PLD, SPLD, GAL, CPLD, FPGA Design :: 13 Sep 2009 15:59 :: naz56 :: Replies: 5 :: Views: 1950
fpga tools- sending/receving data through usb-jtag interface
sahello everybodyi need tool (matlab, labview, .....) to help me in sending/receving data from/to computer to/from fpga board (virtex ii pro). but through the usb-jtag interface only.the situation is like that: the fpga board is the channel of certai...
PLD, SPLD, GAL, CPLD, FPGA Design :: 12 Sep 2009 2:10 :: saeeed :: Replies: 2 :: Views: 282
picture of icd3
pic1...
Microcontrollers :: 11 Sep 2009 7:50 :: master_slave :: Replies: 9 :: Views: 1529
jtag cable for cpld
hi, can tell me about jtag cable.i hav to download a code to cpld using jtag cable.i implemented the jtag cable from xilinx site ........ is there any difference between jtag for fpga n cpld........... what different hardware for cpld.... while d...
PLD, SPLD, GAL, CPLD, FPGA Design :: 11 Sep 2009 7:48 :: shashialabur :: Replies: 8 :: Views: 907
float question-3 errors occur in sysnthesizing with leonardo
hello ,i wanted to work with fixed numbers in vhdl(to be synthesible) , so in modelsim i compiled the 3 files in floatfixlib (math_utility_pkg,fixed_pkg,float_pkg) as a new lib named library ieee_proposed.then i wrote the following code :library ieee...
PLD, SPLD, GAL, CPLD, FPGA Design :: 09 Sep 2009 11:30 :: omidsht :: Replies: 4 :: Views: 327
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