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142 Threads found on edaboard.com: Xilinx System Generator
Hello there, I have an image processing design developed in Xiinx system generator and i have exported it as an IP core. But i have problems in sending and receiving image data in SDK. Does anyone work on these lines.? so that i can ask you further..
I have installed xilinx ISe system generator. It has been configured for MATLAB. But when I open system generator, MATLAB is opening and in that when I open simulink, xilinx blockset is missing. Can anybody suggest how to configure xilinx blockset in simulink.
Use xilinx system generator tool set and you can interface Simulink with RTL design. The other way is HDL coder from Mathworks
I am providing a voice signal to the cepstrum algorithm in xilinx system generator. Input is reaching FFT7.1 properly but it is not generating any output. What I am having on scope is just 'x' undefined output. I also took help from the following link for FFT7.1 He
how to store information (values i want to store are 5,6,7,8) in the single port ram cell of system generator in matlab simulink., what is the function of "initial vector value" in ram cell of xilinx single port ram block set ? Don't use simulink, but that "initial vector value" seems like it might set the initial
hello everyone, i'm using a 256 fft core in matlab system generator, i have a bandpass signals from 750mhz to 1250mhz, im sampling at a rate of 1000mhz, for 750mhz im getting a 750mhz(single peak at 192 index value), for a 1000mhz im getting 0mhz, for 1110 im getting 110mhz, 1250 mhz i'm getting 250mhz, can anybody explain how pls??
Hi... I am using FIR Compiler6.2 in xilinx system generator for a LP design..will this block read floating point values?..when i change the 'gateway in' block to floating point..error is saying that Error : Floating-point data-type is supported only for input TDATA ports of Fast Fourier Transform v8.0 block. Error occurred during
Yes it is possible. Before that you have to install vivado system design. By using xilinx system generator you can convert simulink model into HDL
Your code is only readable for xilinx system generator users that have the respective toolchain installed. To see why "doesn't work", we would need to look at the generated HDL.
Hi friends, I know something about xilinx system generator. But the problem is "i don't know how to use it" and By using system generator whether the circuit convert into HDL or not.
Hi, i want to implement different fir interpolator with interpolation rates 5,10,15 by using single fir compiler in xilinx system generator
Ever wonder why you haven't received any responses? Here let me fill you in on why I wouldn't help even if I had the .mdl file you wanted. Can somebody provide A Model of 'Canny Edge Detector' fully made in xilinx system generator. If someone worked on something non-trivial like this, it was likely: 1) fo
Hi friends, I need to know about xilinx system generator. For what purpose we are using that ?? And whether the blocks are modeled using MATLAB or xilinx.. I need to know about these things.. And also for using the system generator whether we have to install separate tool or not??? (...)
hello everyone, i am a student and got a project for "implementation of a channel equalizer for a wireless OFDM according to the IEEE 802.11a and Hiperlan/2 standard." i dont have knowledge about system level design environments for DSPs into FPGAs..,what i have is this ieee paper and nothing else, i was unable to gain knowledge on internet:
hi guys, i have project about adaptive filter, i built a model in system generator based on hldcoderlms,but when i start with first tap of filter the result between hdl coder(simulink matlab) and my model (on system generator) is incorrecrt (or i can say wrong), but i dont know why, please help me PS: if anyone has model (...)
Hi, I am trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite. I find on internet which shows interfacing only through core generator (MIG). Is there a way I can use xilinx core generator to interface through AHB (...)
Hello all, I need to get output of my matlab simulation on spartan 6 XC6SLX150T FPGA LCD display, steps are as follow 1) i run my simulation with xilinx 14.1 system generator, 2) i run the .xise file generated in matlab with the xilinx 14.1, 3)the program get synthesize, implemented design, generated programming file, (...)
Hi every one. I tried a lot to figure out how to implement LMS algorithm by system generator but nothing. Can you guys help me and give me some hint or simulink file for implementing LMS by system generator? I search a lot in xilinx website and I didn`t find any example? If you guys know it please address (...)
hi, I am using xilinx system generator 13.4 for DDC implementation. I am not getting output after CIC 2.0 compiler block. can any one help me how to set parameters in CIC compiler. please help me
I installed a virtual machine. My virtual machine is XP, I am using matlabr2010a and xilinx 13.1 ( system generator 13.1). I get this error when I do Hardware CO-simulation in Simulink. I can play the simulation , but when I generate Hardaware co-simuluation I get this: ERROR: A license checkout has failed for system (...)
Am not clear of ur problem (not working???). But to use xilinx blocks for a xilinx FPGA (synthesise the design), the whole system should have only system generator blocks and not any simulink blocks(within Gateway In and Gateway Out). But for simulation purpose it is fine to have simulink blocks along with (...)
Hi all, I am looking for additive white Gaussian noise generator . I found that the LogicCore is discontinued by xilinx. I would like to try using system generator , but my matlab version seems incompatible with system generator. Can anyone help me some ways , how can I add WGN to my (...)
I am working on a project "FPGA BASED IMPLEMENTATION OF 2D Disrete Wavelet Transform using xilinx system generator" and i need to take transpose of a image in it. As there is no block of xilinx is available for transpose of an image so I have developed the algorithm in verilog and import it in BLACK BOX of (...)
hi if anyone could help out in telling me how to calculate latency in different blocks of system generator while implementing on fpga?
Which version are you using?. I have used some FIR from xilinx sys gen. However did you meet proper input and output sample rate?.
refer the below link it may help..
hi iam using ise 13.2 and matlab 7.11(2010b) ,i have created ROM code using coregen and when i try to import this code into the blackbox it shows error, i have also tried importing the example code available with the xilinx same error persist please help
Any ideas of how can I implement the "resample" MATLAB code in a xilinx system generator design? I want this to implement the pitch shifting audio effect. For any other questions I'm glad to answer. thank you in advance. panospet
Hello, I'm using a Virtex II pro and I want to download a design that includes the FIR block in Sysgen 10.1. As far as I can see here it says that Sysgen 10.1 includes support for Virtex 2 boards and FIR Compiler 3.2. Unfortunately, when I try to generate a bitstream that contains th
Hello, This is my pitch shifting effect implementation 80191, tested and working correctly, during simulation in simulink. But when I download this in my xup virtex ii pro board, it seems that the upsample/downlsample blocks that I used do not work. My output sounds exactly like it is before these two blocks. Any ideas of what
I think I understand... I understand that my first sim: 79136 was wrong - i start first bit when SCL goes low, but I shall start it when it is already low? So I have to increase the SCL period 2x or 4x because I'm not able to start first bit when SCL is already low. It is bocuse SCL period is
I need one help. Please if you able to help me i will be very grateful for your kind help. There is one tool in xilinx, system generator. I have prepare one architecture using blocks from Simulink in it. i am getting good results then i have generate the VHDL code through HDL CODE GENERATION. now i have a VHDL code of the same (...)
It may not be what you want but, if you can design your system with Simulink, you can find corresponding blocks at xilinx Blockset in Simulink. system generator for DSP is usable tool while designing a system. It seems like Simulink however it is synthesizable, optimized because system (...)
Check the "Importing HDL Modules" chapter in "system generator for DSP User Guide" below. (By the way, download xilinx Document Navigator to manage all xilinx documents) :
Hi all, I want to start some work on the xilinx system generator in simulink, any ideas or tutorials/sample projects on where should i start?, also when i made an inverter in simulink using the system generator, it compiled in matlab just fine, but when i try to simulate it in xilinx ISE, (...)
system generator with FPGA on data acquisition boa... - xilinx User Community Forums
Also xilinx and Altera provide system generator and DSP_Builder for Matlab based solutions. You can try your algorithms based on using these simulink interface. Part of your m file designs can also be instantiated as HDL.
Hi Vedika, Are you sure that you have lineced "xilinx system generator 12.1" ....Some time linence issues also create this kind of the way why do you using matlab for xilinx simulation you can use directly ISE ( xilinx software) for coding and simulation.... Good Luck
I tried doing to same initially because HDL programming appeared far more difficult than MATLAB and because MATLAB code snippets are abundantly available, but i failed horribly at it. The xilinx system generator does work but only for certain built in functions of MATLAB. It cannot convert ur customized code MATLAB code to Verilog/VDHL. In (...)
Hello! Hardwareimplementation works fine. My problem is the clock signal. I need the clocksignal in my design and don´t know how to get the signal. (Something like clockprobe). I tried a simple vhdl (with src_clk_1 and src_ce_1) file as blackbox - but it didn´t work. Is there any trick to use the clock signal? best regards
hi all, can anyone help me converting a xilinx system generator block model to a bit file for loading in an fpga?
Hi there, Im new here. Lately, I am now doing my final year project using Matlab, system generator and xilinx Spartan 6 FPGA LX9 Microboard. In my project, I want to convert m-file to vhdl code in system generator and then program the vhdl code into the Spartan 6 FPGA LX9 Microboard. By the way, (...)
There's no significant difference between a xilinx DCM and what other vendors name PLL, also in term of frequency range. The minimum input frequency (actually the minimum PFD operation frequency) is at least several MHz.
Hi! did any one have the solution(Projects) of the DSP Primer xilinx (system generator)? Thanks
I want to convert m file to vhdl code therefore i need system generator but in my matlab 2010 version xilinx blockset is not available. how to download this system generator please help me
and chapter 2 of
hi everyone! how could i generate a sine wave with system generator simulink (xilinx). could someone help me! Thank u Yasine
Currently am working with SMT8246 sundance (WARP ) SDR kit V2. The xilinx system generator is Simulink. without using simulink hdl coder, how can i extract hdl code from simulink model?... How to dump simulink model into fpga board uding Diamond 3L software?
I think the error is related to some of the feedback loops in your design. I have read something about that in the systemgenerator Getting Started Guide. Try searching the xilinx Website for feedback loops related error reports. Otherwise the error report itself gives you the best advice: "Please report this error to (...)
can any help me ,i am implementing ofdm using system generator.I am stuck at one point now,ia want to implement 16 bit qam using xilinx blockset. how can i do this? please,if anone know then reply to this post.