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17 Threads found on edaboard.com: Xilinx Vcs
xilinx ISE is old and so is ISIM, you should refrain from using them. Better would be to use Vivado and its integrated Vivado Simulator. While questa, incisive are much better but xilinx is giving Vivado for free (free version). You still didn't mention if you have funds at you disposal. If you have go for vcs Synopsys. Vivado Simulator (...)
I have a xilinx VHDL IP which I am compiling along with other Verilog and SV design files. I am compiling the VHDL design files first. Prior to compiling the VHDL design files, I have compiled the xilinx VHDL libs using the command: compxlib -s vcs -p /home/shared/Synopsys/I-2014.03-SP1/bin/ -arch spartan6 -dir (...)
My design has Verilog and VHDL modules along with xilinx primitives.There are no problems with the xilinx Verilog libs. I have also compiled all the xilinx VHDL libraries (a dir has been created with the compiled libs and I also have an error free log file. I had used the xilinx command COMPXLIB for compilation of the (...)
DIGGING UP THE OLD THREAD.... Hi dharag, were you able to find a solution to the problem? Actually I am facing a similar problem now, while integrating a VHDL xilinx IP in a Verilog top-level design and compiling with vcs. I have created a separate filelist and compiling whatever us under unisims ans unimacro. # VHDL unisim and unimacro
I cannot figure out why vcs is throwing this error. Given below is the error message and then part of the code where error occurs. vcs error message: Error- Unknown or bad value for genvar /home/dpaul/rev28462_fpga/src/top_modules/axi_interconnect_v1_06_a/ict106_protocol_conv_bank.v, 228 Elaboration time unknown or bad value encoun
Which tool is best for using VERILOG language. Need with simulation. I have been using xilinx ISE, but there are some problems. Please suggest any other tool.
Modelsim is sort of an industry defacto standard. xilinx ISIM is for xilinx parts only and is still not as good as Modelsim Incisive is a Linux/Unix based simulator from Cadance Aldec is a another PC based simulator that competes directly with Modelsim on features. vcs is synopsys' simulator which is very fast and is Unix based (funny (...)
Hi, I'm having problems simulating a project with mixed HDL (vhdl & verilog) I have RTL source code in both VHDL and Verilog, I get the *.ncd file from ISE implementing the design; then I get the *.sdf file and the net list running netgen tool, also I get the compiled libraries running compxlib tool. Until this point there is no problem, but my
Hi dear all, I have a design. I synthesized it Synplify Premier for xilinx Virtex 4 fpga device. I could perform behavioral simulation and post synthesis simulation with vcs simulator. Synplify Premier uses Place&Route tool of xilinx for place and route job. It places and routes without any problem. When I want to perform Post Place and (...)
i want to know whether can vcs compiler read xilinx ip core gen.....
I use vcs to run xilinx ISE post PR simulation, and found sdf_annotate errors: SDF Error: IOPATH annotation not enabled for module X_BUF. ################################################# The X_BUF model codei is as following module X_BUF的代码如下? `timescale 1 ps/1 ps module X_BUF (O, I); param
i.e if a big project in vhdl is done by using xilinx ise simulator then how to add vhdl code to synopsys vcs. In synopsys vcs coding style is some what different when compared to xilinx. just compare counter example in both flows, if u consider synopsys u (...)
Do we need to simulate post synthesis verilog file ?? If so how ??? In which tool we should simulate this , cos when Im simulating the .V file in xilinx it is showing errors ?? In xilinx only do we need to add any library related to Design compiler Thanks in Advance Arun
Running on Windows XP 32-bit ... xilinx told me they are working on multi-threading ISE. It sure would be nice for place-and-route. I've never seen more than one processor core used in ModelSim SE 6.3 or HyperLynx 7.5. MATLAB 7.4 now uses multi-threading in some operations. Hopefully they will add more. I've seen nice multi-threading in ANSYS 1
How to convert xilinx verilog source code to Synopsys source code and the testbench.:?:
FPGA synthsis tool is depend on what's fpga you want to use Altera-->MaxplusII , QuartusII xilinx-->Foundation,
hi which tool u r using. if u r using xilinx ise tool, go to edit-> language templates..u will find the dll component given, include unisim librar