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20 Threads found on edaboard.com: **Xor Check**

Consider **xor** operator...

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-05-2016 13:25 :: FvM :: Replies: **5** :: Views: **511**

Hello all. I finished my layout for an inverter a couple of hours ago and ran DRC and LVS with no errors (they were successful).
I then needed to make a layout for an **xor** gate which used two inverters. After I used the "pick from schematic" option, I instantly ran a DRC **check**, which then gave 228 "Edge not on grid" errors. I know that this error

ASIC Design Methodologies and Tools (Digital) :: 11-11-2013 07:00 :: theelder777 :: Replies: **1** :: Views: **704**

Some might argue that certain steps in crypto are hard to reverse on purpose. This might be one of those cases.
Case in point, without extra boundary conditions (i.e extra knowledge about the system) x **xor** (x<<6) **xor** (x<<10) might well be irreversible.
Edit: Did a quick **check**. I stand corrected by myself. It has an inverse. :P

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-30-2013 09:49 :: mrflibble :: Replies: **1** :: Views: **834**

You must **check** all possible input combinations.
No matter what the function of a combinatorial digital circuit is. AND , NAND, OR, **xor**, etc.
The number of input combinations is 2 to the power of number of inputs
i.e:
inputs -> comb
1 -> 2
2 -> 4
3 - > 8
4 - > 16

Elementary Electronic Questions :: 09-23-2012 18:08 :: albert22 :: Replies: **7** :: Views: **895**

hi,
explain BILBO shift right register and use one **xor** to generate parity or after shifting the data from left to right using several d flipfop , how to **check** for parity by using single **xor**.

ASIC Design Methodologies and Tools (Digital) :: 12-16-2011 04:36 :: tulsi :: Replies: **0** :: Views: **656**

Also, I see that there are 5 pins on the **xor** component I only expected three :-S
There are 3 pins for logic as you expected, but you probably forgot about powering the component, that's what other two pins are for.

Elementary Electronic Questions :: 10-13-2011 13:04 :: this :: Replies: **5** :: Views: **1276**

In our project we have a PLL which outputs two clocks and they are **xor**-ed to generate a clock with 2x higher frequency. When we do STA, we have problem because when creating generated clocks doubling clock isn't supported, so we can't get the delay from PLL and through the **xor** gate propagated automatically.
Is there anyone who did this as well?

ASIC Design Methodologies and Tools (Digital) :: 02-21-2011 08:40 :: jason-zyx :: Replies: **2** :: Views: **1069**

Basically, an **xor** gate with one input delayed can achieve this. You have to **check**, if it's feasible with your available logic.

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-04-2010 08:41 :: FvM :: Replies: **2** :: Views: **2657**

- The conversion from "offset binary" to two's complement is done by inverting the MSB (respectively performing **xor** x"8000") rather than substracting -32767. You can **check**, that the latter produces an overflow for full scale input of x"FFFF".
- The multiply result has 16 + coef_int'length bits, so you can't use it for an 16 bit output without ca

PLD, SPLD, GAL, CPLD, FPGA Design :: 09-04-2009 22:13 :: FvM :: Replies: **1** :: Views: **3820**

The CRC division is not numeric. It is polynomial division with Boolean coefficients. The LFSR technique is a direct translation of the polynomial division, using **xor** to do the "subtraction".

PLD, SPLD, GAL, CPLD, FPGA Design :: 06-20-2009 21:23 :: tkbits :: Replies: **6** :: Views: **3794**

The magic of **xor**. Scroll down to parity **check**.

ASIC Design Methodologies and Tools (Digital) :: 03-16-2009 22:26 :: Digital-L0gik :: Replies: **2** :: Views: **3810**

TWmin = 54ns
In setup we use the slow corner. Trace one of the paths through the **xor** (they are both identical) and demand that the signal arrive at the D pin of the first FF 6ns (tsu) before the next clock tick arrives. This gives you:
tPINV + tPFF + t**xor** =< TW - tsu
12 + 14 +22 =< TW -6
TW >= 54
Let us now **check** to (...)

ASIC Design Methodologies and Tools (Digital) :: 08-16-2008 18:07 :: MarcS :: Replies: **1** :: Views: **3222**

let transmitted word =
let noise =
rcvd word = ( X = **xor**)
we find syndromes at reciever:
S1 = r2 X r5 X r4
S2 = r1 X r4 X r3
S3 = r0 X r5 X r3
take S1 for example
S1 = (t2 X n2) X (t5 X n5) X (t4 X n4)
but from encoding schem

Digital communication :: 02-18-2008 13:48 :: bulx :: Replies: **1** :: Views: **1078**

a **xor** b = (NOTa AND b) OR (NOTb AND a) ,this is what I know, but you can chek it again :)
about memory mapped I/O you can **check** here
it's pretty straightforward

Embedded Linux and Real-Time Operating Systems (RTOS) :: 07-26-2007 01:52 :: mitaka :: Replies: **2** :: Views: **884**

You mean 2 bit full adder !!!
well attached is a powerpoint p;ease **check** it if you need help be more precise:
full adder input: A,B,C output S and Cout
Cout= AB + CB + AC
S = (A' B + A B') **xor** C
= (A **xor** B) **xor** C
O...sorry
How about 2- bit full adder??
I can nit find in the powerpoint attached file

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-07-2007 10:31 :: cyw1984 :: Replies: **4** :: Views: **12287**

It's a shift register plus a few **xor** gates and maybe some steering logic.
Here is a Xilinx app note example: "IEEE 802.3 Cyclic Redundancy **check**"

Digital Signal Processing :: 12-01-2006 05:54 :: echo47 :: Replies: **1** :: Views: **1045**

Dear,
I want to design a combinational circuit hat compares two 4-bit numbers to **check** if they are equal. The circuit output is equal to 1 if the two numbers are equal and 0 otherwise.
u can use 4 **xor** gate and combine all the four output of **xor** gates in a 4 input NOR gate and the output of this NOR gate is the required output.

Hobby Circuits and Small Projects Problems :: 10-03-2006 10:42 :: nikhilele :: Replies: **5** :: Views: **14323**

In 8051 family, there is an aintruction CJNE. With this instruction we can **check** the two values, smaller, equal, or greater.
In PIC how we can do the same function?
Can we **check** if W reg. is zero or not (Like JZ or JNZ in 8051).
If yes then i think we can **check** the 2 values of W and L or F by using **xor** instruction.
But (...)

Microcontrollers :: 10-21-2005 15:26 :: Noman Yousaf :: Replies: **3** :: Views: **1673**

i try to explain.... but mayb i am wrong... **check** ur textbook for further details
the compiler **check** for errors... then it create netlist(in a process call synthesis)
vhdl is inherently concurent.. which mean tht the code sequence has no different
g<= a and b;
h<= a **xor** b;
or
h<= a **xor** b;
g<= a and b;
is the (...)

Elementary Electronic Questions :: 07-26-2005 04:27 :: sp :: Replies: **4** :: Views: **1510**

you could try and catch an edge on the data line using FF and **xor**...run a counter between to edges and **check** the count.

ASIC Design Methodologies and Tools (Digital) :: 02-21-2005 21:07 :: peen1 :: Replies: **3** :: Views: **1446**

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