33 Threads found on edaboard.com: Xor Cmos
Please can any body tell me how to implement xor gate using cmos in verilog ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.01.2008 04:41 :: pareshatlnmiit :: Replies: 2 :: Views: 1941
Is that possible to design a xor gate using only 6 transistors
pls let me know
ASIC Design Methodologies and Tools (Digital) :: 31.08.2007 03:02 :: santuvlsi :: Replies: 8 :: Views: 3122
I want to increase the drive of the circuit in case of opposite bit patteren
You mean you want to increase high-level driving capability of xor? Because for opposite input pattern xor output is HIGH.
a simple buffer/inverter
What exactly: Buffer or inverter?
Buffer in contrast to inverter has opposite logic
Analog Circuit Design :: 10.09.2007 05:26 :: Fom :: Replies: 14 :: Views: 768
how to realize a xor gate?/ thanks
Analog IC Design and Layout :: 18.10.2007 06:33 :: benever :: Replies: 8 :: Views: 4379
I think static power dissipation is less for cmos
and u use transmission gate to transfer proper 1 and proper 0 to the output........
Instead of making xor gate with cmos u go for transmission gate technique..................
ASIC Design Methodologies and Tools (Digital) :: 03.11.2007 13:41 :: mujju433 :: Replies: 2 :: Views: 653
hi friends, i got to know that there are many architectures are existing for xor gate out of those i know only one, ie AOI(and or not)
can anyone please introduce some other arch for xor to me
Electronic Elementary Questions :: 26.01.2010 12:05 :: rajatbvb :: Replies: 0 :: Views: 847
implement NAND and xor using cmos in xilinx?
you cannot implement NAND and xor "using cmos" in xilinx.
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.11.2010 04:11 :: srizbf :: Replies: 7 :: Views: 1269
can any one help me to implement xor using cmos logic? i know how to implement it using transmission gate.. need to know it at transistor level..
Electronic Elementary Questions :: 03.04.2011 23:46 :: kruchi_19 :: Replies: 4 :: Views: 5365
Please, could you clarify me the following confusion regarding Static cmos logic?
In the Rabaey book, it is said that "Static cmos gate is naturally inverting and the realization of a noninverting Boolean function (such as AND , OR, xor) in a single stage is not possible."
I don?t completely understand th
Electronic Elementary Questions :: 19.05.2011 08:18 :: palmeiras :: Replies: 3 :: Views: 693
For making xor gate you can make use of 8 gates, 4 pmos and 4 nmos using simple relation for xor= (~A)B+A(~B)
As far as 2:1 MUX is concerned, there are many options. You can use NAND gate, Transmission gates, pass transistor.
ASIC Design Methodologies and Tools (Digital) :: 21.11.2011 13:41 :: abhiverma812 :: Replies: 6 :: Views: 5579
Yes, it's a trans gate. And the function is xor.
ASIC Design Methodologies and Tools (Digital) :: 11.01.2012 03:59 :: Kaisia :: Replies: 4 :: Views: 749
How many no. of nmos and pmos transistor are require, for xor logic gate implementation?
a)2 nmos And 2pmos
b)3 nmos And 3pmos
c)6 nmos And 6pmos
d)8 nmos And 8pmos ?
I am confused, please tell right answer....
ASIC Design Methodologies and Tools (Digital) :: 18.04.2012 08:47 :: Urvashi :: Replies: 4 :: Views: 4339
use xor logic, or counter
Digital Signal Processing :: 22.08.2004 10:16 :: claint :: Replies: 6 :: Views: 1021
I know a cmos xor/Xnor gate can be implemented with 10 transistors, but I don't know whether or not this is the lower limit for the number of transistors.
Electronic Elementary Questions :: 21.10.2004 23:48 :: Hughes :: Replies: 17 :: Views: 1944
Normally you design an inverter to have equal rise and fall times. This is the most general approach. Minimum channel length can be used if you want to reach maximum speed. Channel widths depend on the drive strength you want to have for a given maximum speed.
To design a any other gate function, once you have the inverter designed, transistor c
Analog IC Design and Layout :: 27.10.2004 03:21 :: Humungus :: Replies: 8 :: Views: 4728
I am doing a school project which involves designing a 4-bit LFSR (one xor in the front that is fed from the last 2 FF's) using 0.18u in Cadence. The goal is to make it as fast as possible, without consideration of area or power. We decided to use C2MOS (Clocked cmos) for our flip flop's, and have reached a clock speed of about 3 GHz. It se
ASIC Design Methodologies and Tools (Digital) :: 24.07.2005 12:54 :: jdhar :: Replies: 7 :: Views: 1015
Nangate Cell Compiler ( )
Compiling the optimal set of individually optimized cells for a given design or functional block, the target design is optimized in terms of power, performance and area.
- 1) Rich set of cmos logic cell gen
ASIC Design Methodologies and Tools (Digital) :: 06.04.2006 01:25 :: joe2moon :: Replies: 17 :: Views: 6212
use a delay then xor the delayed with the undelayed.
the pulse width is the delay unit used
Analog Circuit Design :: 30.05.2006 11:41 :: safwatonline :: Replies: 3 :: Views: 1709
Please don't confuse a digital PLL with a PLL that uses digital circuitry in its phase detector (PD).
Certain types of PDs for analog PLLs are based on xor gate or flip-flops, but these PLLs are still analog: VCO and loop filter are analog.
A digital PLL is all-digital. It is discrete-time (sampled) in nature. It has a NCO instead of a VC
Analog Circuit Design :: 22.09.2006 11:55 :: zorro :: Replies: 8 :: Views: 3619
1. please clarify more clearly no 1. questions.
2. using logic to generate fast clock? you can use delay cell to delay a clock and then xor the origin clock and delayed clock. but be careful do that becoz it's need more design exprience.
ASIC Design Methodologies and Tools (Digital) :: 23.10.2006 01:54 :: linuxluo :: Replies: 4 :: Views: 474
A full adder has 2 xors, 2 ANDs and 1 OR gate.
Each xor has 2 ANDs and 1 OR and 2 INVs
So we have a total of 6 ANDs and 3 ORs and 2 INVs
ANDs and ORs use 6 transistors in cmos, INVs use 2 transistors
So, 6*(6+3) + 2*(2) = 54 + 4 = 58 Tranistors
Hope I got that right!
ASIC Design Methodologies and Tools (Digital) :: 05.03.2007 08:13 :: Arturi :: Replies: 16 :: Views: 2287
This is my first time in here,so I don't really know this thing works.
I have a question regarding a simple PLL in cmos which consist of a xor gate and negative-Gm LC oscillator whose frequency is tuned by varactor diodes. I am not really sure how the frequency of oscillator changes. can some one explain the process to me or maybe g
Electronic Elementary Questions :: 17.05.2007 12:56 :: vakil :: Replies: 3 :: Views: 910
Its well known that all gates can be derived from NAND and NOR gates...But is it that in all digital IC's are other gates like AND ,OR and xor gates are made up of NAND and NOR gates... does the other gates have seperate circuit using less number of transistors...
Electronic Elementary Questions :: 01.06.2007 12:19 :: lordsathish :: Replies: 3 :: Views: 1268
For Lock Detector
just use xor gate with inputs up & down (PFD outputs) if the PLL at lock the up & down will be identical & the xor will stick to 0 other wise the xor will toggle
you can use DFF & samples the xor out with the reference frequency
Analog Circuit Design :: 31.10.2007 12:07 :: rania_hassan :: Replies: 4 :: Views: 582
The question is " Is there any paper, book etc that describes the tradeoffs between area, power and performance when you choose different logic styles to map a logic?"
for example a given logic can be mapped on to mixture of cmos gates which might include AND, NAND, NOR, OR, INVERTER,xor, XNOR etc. What would be the tradeoff if i force the logic
ASIC Design Methodologies and Tools (Digital) :: 06.06.2008 14:23 :: tariqbashir786 :: Replies: 2 :: Views: 531
FPGAs not only have LUTs but also basic AND/OR/xor etc. gates, depending on the vendor, model etc. Take a look at this article for more details. (If you also take a look
at an FPGA STA report you will see that gates other than LUTs are present with much smaller delays).
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ASIC Design Methodologies and Tools (Digital) :: 26.08.2008 04:56 :: pmat :: Replies: 6 :: Views: 605
I am having a problem with my simulation result when I designed the OOK Manchester capacitive load modulator for 13.56MHz RFID tag according to ISO14443 Type A standard. The followings are my circuit design for the modulator and the simulated result by using Mentor Graphic software TSMC 0.18um technology.
RF, Microwave, Antennas and Optics :: 03.12.2009 04:48 :: flying_fish :: Replies: 0 :: Views: 2720
this is my nor2 gate code.i need to calculate power with hspice and estimate power with formula myself.with hspice simulation power=8.2902E-06.and i calculate power with this xor and nand gate i can calculate power with less difrence with hapice result.but in nor i dont khow how i must calculate it?this
Analog IC Design and Layout :: 26.08.2011 08:23 :: diod :: Replies: 1 :: Views: 540
I hope you already know what is "the standard cells library". If not in two words: the standard cell library is a set of difference type of general purpose gates,flip-flops etc. for example NOR, NAND, xor, INV. Also possible 3 input NAND, NOR etc, library could include 2X, 3X... NAND or NOR gates, where 2X mean gate can pass 2 time bigger current.
ASIC Design Methodologies and Tools (Digital) :: 16.10.2011 16:20 :: mkrtich.nazaryan :: Replies: 3 :: Views: 591
Just wondering what a typical ALU looks like? From what I was able to find, it generally consists of an adder and some logic (AND, OR, xor) between two flip-flops and with a mux to decide which output to take - is this correct? Also, does the adder and logic both evaluate every cycle. If only the logic is needed, for example, is it not wasteful to
Digital communication :: 05.03.2012 12:29 :: tasctasc :: Replies: 2 :: Views: 308
I am trying to design an xor gate...but the instructor has asked us to merge two pmos transistors in the design...
kindly provide me the solution...
I am using cadence 6.1.5
ASIC Design Methodologies and Tools (Digital) :: 02.06.2012 14:34 :: pavanucs :: Replies: 4 :: Views: 520
When I was in R&D back in mid 70's our techs at Bristol Aerospace used simple triac controlled 25W irons to control temperature that were left on all day, typ. 65%.
- Later when Weller had fancy temp controlled irons, these were preferred.
- But triac control is cheap, but your method is quicker to startup.
- I would choose a therma
Show DIY :: 19.06.2012 14:58 :: SunnySkyguy :: Replies: 2 :: Views: 953
i am designing a simple phase locked loop with only cmos chips CD 4007, i have built it before and worked fine. however i did something wrong to make it work. now i am reassembling it and i was not able to get it work. i am using an xor for my phase detector , i tried using both a passive RC filter and a passive lead lag RC filter
RF, Microwave, Antennas and Optics :: 12.10.2012 23:54 :: rnz1991 :: Replies: 1 :: Views: 177