15 Threads found on edaboard.com: Xor Cmos
1. I'm simulating 8 bit mips processor from cmos VLSI DESIGN: 4th Edition. This is results that I obtained for Astro and VCS using Synopsys. I've no problem with Astro but for VCS simulation, at the first instruction, the result is ok but when it proceeds to second instruction, there is something which I not quite understand. Why the me
ASIC Design Methodologies and Tools (Digital) :: 06-22-2015 04:47 :: deepsetan :: Replies: 0 :: Views: 322
I modelled an xor gate using HSPICE (Transistor level).Input voltage signal is 4V and Vdd of the circuit is 5V (threshold voltage= 1v).
While giving input voltage 4v I got Maximum output voltage swing as 5v, So my problem is I cant cascade the output of this xor gate(5v) with another xor gate beacause it will turn off cascaded transistors. (...)
Analog Circuit Design :: 06-05-2015 17:11 :: gstekboy :: Replies: 3 :: Views: 512
Hi everyone hope you are all fine.I am new here please help me.I want to implement 1 bit full adder using Nano cmos BSIM MOdel in LTspice.
Adder has two outputs Sum and carry out
Sum is equal to X-OR of three inputs A,B and Cin It means i need to implement two xor i have implement X-Or Using BSIM model in Ltspice Separate and they are wo
ASIC Design Methodologies and Tools (Digital) :: 07-03-2014 20:00 :: Fasi477 :: Replies: 0 :: Views: 642
As per my Knowledge you need 12 transistors to implement xor gate......,6pmos,6nmos transistors are required.....,
Hope This Can Help You.....,
ASIC Design Methodologies and Tools (Digital) :: 04-29-2012 14:47 :: firstname.lastname@example.org :: Replies: 4 :: Views: 13115
Yes, it's a trans gate. And the function is xor.
ASIC Design Methodologies and Tools (Digital) :: 01-11-2012 08:59 :: Kaisia :: Replies: 4 :: Views: 1254
For making xor gate you can make use of 8 gates, 4 pmos and 4 nmos using simple relation for xor= (~A)B+A(~B)
As far as 2:1 MUX is concerned, there are many options. You can use NAND gate, Transmission gates, pass transistor.
ASIC Design Methodologies and Tools (Digital) :: 11-21-2011 18:41 :: abhiverma812 :: Replies: 6 :: Views: 16875
Please, could you clarify me the following confusion regarding Static cmos logic?
In the Rabaey book, it is said that "Static cmos gate is naturally inverting and the realization of a noninverting Boolean function (such as AND , OR, xor) in a single stage is not possible."
I don?t completely understand th
Elementary Electronic Questions :: 05-19-2011 12:18 :: palmeiras :: Replies: 3 :: Views: 1792
implement NAND and xor using cmos in xilinx?
you cannot implement NAND and xor "using cmos" in xilinx.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-28-2010 09:11 :: srizbf :: Replies: 7 :: Views: 2283
well i am not sure but iguess you could implement the cmos in verilog and then map it... to form xor... cmos can be implemented just as a NOT gate or you could also implement as VTC curve...
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-31-2008 22:41 :: haneet :: Replies: 2 :: Views: 3062
hi friends, i got to know that there are many architectures are existing for xor gate out of those i know only one, ie AOI(and or not)
can anyone please introduce some other arch for xor to me
Elementary Electronic Questions :: 01-26-2010 17:05 :: rajatbvb :: Replies: 0 :: Views: 1217
FPGAs not only have LUTs but also basic AND/OR/xor etc. gates, depending on the vendor, model etc. Take a look at this article for more details. (If you also take a look
at an FPGA STA report you will see that gates other than LUTs are present with much smaller delays).
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ASIC Design Methodologies and Tools (Digital) :: 08-26-2008 08:56 :: pmat :: Replies: 6 :: Views: 989
For Lock Detector
just use xor gate with inputs up & down (PFD outputs) if the PLL at lock the up & down will be identical & the xor will stick to 0 other wise the xor will toggle
you can use DFF & samples the xor out with the reference frequency
Analog Circuit Design :: 10-31-2007 16:07 :: rania_hassan :: Replies: 4 :: Views: 891
how to realize a xor gate?/ thanks
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-18-2007 10:33 :: benever :: Replies: 8 :: Views: 10403
Is that possible to design a xor gate using only 6 transistors
pls let me know
ASIC Design Methodologies and Tools (Digital) :: 08-31-2007 07:02 :: santuvlsi :: Replies: 8 :: Views: 5738
This is my first time in here,so I don't really know this thing works.
I have a question regarding a simple PLL in cmos which consist of a xor gate and negative-Gm LC oscillator whose frequency is tuned by varactor diodes. I am not really sure how the frequency of oscillator changes. can some one explain the process to me or maybe g
Elementary Electronic Questions :: 05-17-2007 16:56 :: vakil :: Replies: 3 :: Views: 1226