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Xor Gate Using Cmos

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Please can any body tell me how to implement xor gate using cmos in verilog ?
Friends Is that possible to design a xor gate using only 6 transistors pls let me know santu
Thus to make a xor by this way u need 8 2x1 MUX ! 3 2x1 MUXes should be enough to build ANY 2-inputs gate. First of all, you can build 4x1 MUX from those 3 2x1 MUXes. And then use the same approach as LUT in FPGA, by providing constant 1s and 0s on MUX inputs, that correspond to output column of truth table for desir
Can anyone tell me how to design a xor gate using 2:1 Mux and an inverter. I have tried all ways and couldnt find a solution. Thx radhika
hi frens can anyone tell me how to implement nor gate using cmos transmission gate... urgent!!!
What is the simple logic to make xor gate using multiplexer? urgent Bye take care
Yes, it is not possible to implement a xor gate without using any inverters. But I think you need two different circuits as shown in the attached figure (though that's not what your prof
I am designing cmos logic xor gate and 2:1 multiplexer. In my design i am using 8 pmos and 8 nmos for 2:1 mux and 6 pmos and 6 nmos for xor gate. I am using pmos and nmos to implement complement A, means that i am not using complement directly into the (...)
how to realize a xor gate?/ thanks
HI, How to derive xor gate using 2:1 mux and 1 not gate? -P
how to design an AND gate from xor gate.
hi help me to implement two input OR gate using xor gate.. Thanks in advance praveen.S
I cant come to the solution that how can i implemen the xor gate if i only have "and" and "or" gates or if i have to subtract bx from ax without using xor and sub memonics then how can i do that please any one help me i shall be very grateful to him
Hello, I need a BPSK modulator and demodulator circuit using xor gate.Please help me. Thank you
Is it possible to fabricate a component having the functionality of a capacitor using cmos transistors ?
A NOT gate is an inverter. Use the xor with one input tied high.
How can I implement a simple NAND or NOR or NOT gate using commercial 3-pin transistors? e.g. how many would I need (2 I assume?), where would each pin go to, etc... I know I can use IC's but I want to build one using transistors. Thanks.
whats the delay of a xor gate ?
can anybody tell how to design a+(b+c)'+c using cmos ....2nd term b+c)' is nor gate but how to add a+c with nor that i don`t understand
can anybody tell how to design ( a.(b+c))' using cmos
hi friends, i got to know that there are many architectures are existing for xor gate out of those i know only one, ie AOI(and or not) can anyone please introduce some other arch for xor to me
Hi, I'm looking to build a 3input xor gate that minimizes EDP. I've been looking through web and found some some enticing
Hi there, I am deal with the And-Or-Invert (AOI) of the xor gate. But I not sure what I draw is appropriate or not.
Hello, I'm looking to build a 2x input OR gate and a 3x input xor gate using Resistor/(NPN)Transistor Logic. I have this schem of a 3x Input NOR: From that schem, if I remove 1x Input and either Invert the o
Does anyone has experience in RFIC design using cmos process? Or some exp in A_D_S or S_pectreR_F in RFIC dsign? I am freashmen in this field. Does anyone want talk about this? :smile: ^^.
hi, can we use load line matching if you developing power amplifier in IC using cmos process
Hi Is it possible to make a Not gate using 2x1 Multiplexer. If yes, HOW? if no, Why?
May i know where can i find good references (books,article) for designing active inductor using cmos technology? Thanks. Added after 14 minutes: sorry... one addition question about active inductor. i forgot ask just now. If i simulate active inductor using T-spice (BSIM3 model, 0.35 cmos technology)
Hi frds, Help me to design a NOR gate using THREE tri-state inverters and wired-AND logic should not be used. Thanks Regards,
Hello how can i make an xor gate with some diods and resisors? Thank you
hello, does any one have got any papers about relax osc using cmos to generate SQ wave and triangle wave with hig freq's
Can somebody give me papers/reports on design of High Current(>50mA) charge pump Voltage doublers using cmos? I have tried looking on the web but all I can find is PLL charge pumps which use very little current. I need one for very large current? Thanks Suhas
plz help me out in design of mod 5 counter and deccade counter using cmos
how to design a zener diode in IC using cmos process? Could I just build in a diode and bias it in reverse bias? The zener diode requirement is about 18V.
i want to know how to implement tanh function using cmos and how to implement exponential and logarithmic amplifier using cmos except the transistors are in weak inversion region
Hello all, I am now designing a SiGe HBT ECL xor gate. When I simulate my xor gate, I tend to get the high glitches (see picture) in the transcient simulation. Can anyone tell me how to reduce those high glitches. I greatly appreciate for your help. Thanks, chemaphy
can somebody plz tell me how to write the xor gate program in e language??
Hello, I used to know this in school, but can't recall it now. I know that a two-input xor gate gives a high output when the inputs are different. But, what about a multi-input xor gate and a multi-input XNOR gate. Any help would be much appreciated.
hi Guys, Could anybody please tell me how to implement a 19 input xor gate with 2 input xor gates? Thank you.
Hi does anyone know a site for digital circuits using cmos inverters
I want to design a desired notch filter using cmos devices. Can anyone give me the resources available and the method.
Why don't you simply use a VHDL xor operator?
Hi friends Please tell me how to calculate delay for an 2-input NAND gate using spectre calculator.NAND gate has two inputs and one output.between which input and output i have to take the delay.how to do this .How to calculate leakage power and dynamic power using spectre calculator.Please help me its very urgent in my (...)
Gooday, I am trying to implement a multiple input XNOR gate using the virtex II Pro unisim primitive BUTF. My VHDL code is as follows: library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity BUFT_XNOR is port ( E_0, E_1, E_2, E_3 : in std_logic ; enable : out std_logic ); end BUFT_XNOR ;
Gooday, I am trying to implement a multiple input XNOR gate using the virtex II Pro unisim primitive BUTF. My VHDL code is as follows: library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity BUFT_XNOR is port ( E_0, E_1, E_2, E_3 : in std_logic ; enable : out std_logic ); end BUFT_XN
i am newbie to micro world pls how to make and gate using 89s51 if all input are high output is high so fren how to start here is my code switch1 equ p2.0 ;input switch 1 switch2 equ p2.1 ;input switch 2 switch3 equ p2.2 ;input switch 3 switch4 equ p2.3 ;input switch 4 switch5 equ p2.4 ;input switch 5 switch6 equ p2.5 ;input swit
hello friends i have to design a gilbert multiplier using cmos.but i have a problem in atlas code. i am designing this ckt in mixedmode using atlas simulator.plz tell me hw to write a code in mixedmode.give me a example of this type of ckt.
hello i need to design encoder used to convert thermocode to binary code in flash adc which is a priority encoder using cmos can any one give an idea for me thanku
Why only xor gate used in DFT compression logic ?
I've been working on a circuit using cmos 4013 Flip-Flops. Can I feed power to these circuits directly from a 15 amp circuit in the vehicle without any type of conditioning and/or current limiting circuit? Can I also use a direct connection to a switched power source like the lights or horn to trigger and reset the 4013? I want to make sure I do