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Xor Gate Using Cmos

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4 Threads found on edaboard.com: Xor Gate Using Cmos
I modelled an xor gate using HSPICE (Transistor level).Input voltage signal is 4V and Vdd of the circuit is 5V (threshold voltage= 1v). While giving input voltage 4v I got Maximum output voltage swing as 5v, So my problem is I cant cascade the output of this xor gate(5v) with another xor (...)
Hey, For making xor gate you can make use of 8 gates, 4 pmos and 4 nmos using simple relation for xor= (~A)B+A(~B) As far as 2:1 MUX is concerned, there are many options. You can use NAND gate, Transmission gates, pass transistor. Best Regards, Abhishek
well i am not sure but iguess you could implement the cmos in verilog and then map it... to form xor... cmos can be implemented just as a NOT gate or you could also implement as VTC curve...
Friends Is that possible to design a xor gate using only 6 transistors pls let me know santu