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i need some way to let my microcontroller know when a zero cross occurs, otherwise i cant keep phase with my little light dimming project. i saw plans for using a 4n25 (the most primitive of optocouplers: merely a transistor pretty much), but i havent had much luck actually making it go. it pretty much just hooks the LED input up to the AC
The descprepancy might originate from your hand calculation is not accurate enough: the Cgd of the input transistor is not easily calculated by hand. You should rely on the simulator to give you more precise number. A sanity check also reveals that the zero can not be at over 100GHz frequency. 40~50 GHz is a more reasonable number. Willy
Give here ur VHDL example for weak zero. I will write equivalent verilog for that!
Here are some other examples of zero crossing detectors .. Regards, IanP
Hi, If you are talking about power line zero crossing, then have a look at microchip application note AN958, you will find the answer there. Good luck.
When trying to intutively understand how a zero occurs in a circuit... For any zero I am of the understanding that for a finite Vin ==> the ouput Vout(Sz) =0 Now, if I apply a signal at the input then In a common source stage: Intutively, The feed-forward path(thru Cgd) and the main transistor path bo
Magnetic field outside a long solenoid can never be zero. Because a solenoid of finite length will have edges and field will come out. However, if we imagine a straigth solenoid of infonite length or a toroid, it will not have edges from where lines of force can come out. therefore field would be zero outside a toroid or a strigth solenoid of infil
Hi all i need a code for zero forcing algorithm to supress interference plz help Thanks
hey u means ∂^2 π=0 na? then well i dont know the exect derivation but del= partial derivatives... and the pie is a if u go for double derivatives of pie it will be zero only.. that was as per the best of my knowledge... best luck..
Dear friends!. I want to make transformer based power supply. I used 12-0-12 transformer. I want to get 24V from both end. after that 24V to 5V. in the mean time I am also want square wave for zero cross detection. I put 230VAC on primary winding. we already know that there is a phase shift between primary and secondary of tra
Hi, all I want design a Return to zero optical link with variable duty cycle. I started it from 50% duty cycle. Following is my block diagram. Basically, I use a and gate to generate 50% duty cycle Return to zero(RZ) signal and use D flip flop to recover the signal to Non-Return-zero.
I just un-installed my MatLAB otherwise i would have checked it properly. Adding a zero z will change the root locus plot of the system. Its may be the reason that when we convert open-loop system to close loop. z will be introduced in denominator. Which will change the response of the system. Plot your system here users.ece.gatech.ed
how to make a zero crossing detector circuit using 8051
Hi Thanks. I searched for APC-7 on their site with zero results. They only mention a 7mm to N adapter. I will email them to find out what it is.
In the analog world a method that is within 1 dB of optimum is 1. Slice the base band data signal to get hard limiting 2. Low pass with a 1 pole filter at 3/8 of the bit rate 3. Square (full wave rectification will also work but is a few dB worse 4. Filter out the spectal line at the bit rate Can this be approximated in your FPGA?
you just need an IR Led for transmiter and a photodiode for reciver. This way you can build the electrical interface of IRDA. Next, you need to write a few lines of code yn your mcu for inplement a much like software uart. Main difference are that IRDA signals are zero Return (ZR) insted of RS232, wich are Non zero Return (NZR). I've implement
Many thanks for replies. :) So problem is: I need to limit current from both side(zero current detection and current limiting). I look thourght you suggestions... so i need some thing cheapest. May be i can simply use something like LM324 to get diferencial signal from sensing resistor? Are there any other suggestions Best regards, kot_b
Hi, If power is a real issue, you can use a zero power or low power version GAL, or switching to a zero Power CPLD. Lattice has now ultra low power (10?A) standby CPLD.
You first have to make a zero cross detector, as you may want to start sampling at zaro-crossing.
If no current source is used ,the output oscillation swings between -Vdd and Vdd. If a current source is added the oscillation amplitude will be equal to IbiasXRtank (for IbiasXRtank
>> help find FIND Find indices of nonzero elements. I = FIND(X) returns the indices of the vector X that are non-zero. For example, I = FIND(A>100), returns the indices of A where A is greater than 100. See RELOP. = FIND(X) returns the row and column indices of the nonzero entries in the matrix X. Thi
Hello everyones ! I'm a new member on this forum. I come from Vietnam as a electronics engineer. I've tried to design a RTOS kernels on 89c52 with 8KB ext RAM. It just the way to learn Real-time Linux. My evalution board consist a 89c52 with 8K RAM (6264) at 0x8000. There are 16 task in my design, each task has a 256 bytes external memory.
Definately, you can set up the initial condition. Usually the circuit which needs a start up has two stable operating conditions, one at zero volts and the other at the normal voltage at which the circuit operates. Hence, the start up is used to push the circuit to the second stable operating condition by pumping the required current. So, you can
There is an easy way to achieve zero phase error that is to use "zero dely buffer" ic. It's a common device available from some manufacter such as ICS, Cypress. If you wanna design one by your self, then you have to considering the addtional phase error between the reference divider and output divider. An useful way to solve this problem i
thanks it should have the power-on-reset,and powe-down-reset function, and when reset is down it should consume zero-power!! thank you very much
When you connect the chip, make sure that the power supply is giving you 'zero' current. Increase this slowly. don't start off with vdd set to give you unlimited current. Run a DC open/short on the chip itself when it is not mounted. Run a DC open short test on your PCB FIRST!!! Use an antistatic wrist-band OR touch the properly grounded i
Hi bleach: at first and for simplicity you suppose that you are simulating a BPSK transmitter and reciever and you are going to plot the BER versus SNR. so you should do these three stages : 1. you should generate a sequence of binary data which are in form of BPSK , such as this sequence {1 -1 -1 1 1 1 -1 . . .}. 2. you should combine the
The simplest way to set the span to zero of spectrum analyzer and sweep time should be very slow regarding to normal sweep time. If you know exactly the frequency of synthesized, you set the center of spectrum analyzer, set the span to zero and slow down the sweep. if you can, you may apply a trigger signal to start-up the sweep. Or, simlpy conn
a question for those engineers out there. I am looking for a verilog digital circuit that outputs a 1 as long as clock is running and outputs a zero if the clock stops. anyone knows how to do this.
Hey, I'm a 3rd year student of electronics and I need help to design a circuit that receives a sinal V0 with respect to the ground and outputs: 1) V0 in pin A and 0 (zero) in pin B, if V0>=0; 2) 0 (zero) in pin A and V0 in pin B, if V0<0; Any ideas how to implement this circuit?
First of all , what i suggest is to make sure you want to get into ASIC job, coz you joined SF QA and now you are realising that you wana change. That might repeat with ASIC. But if you are really interested in working in ASIC, remember you got to start from zero. As your QA experience won't count. Go for some placement and job oriented courses.
hi every body when i try to make interupts on this pic the pic operate for some time ( high and low on RB7) and then reset ( i see it on oscope) it do fine for 2 seconds and then reset to zero for one second could u plz help me
The gate drive of SCR will have a low impeadance. The work off of current to drive them not voltage like a FET. You should probably be hitting about 1-1.5 V peak on the gate drive of with the SCR connected. The attached drawing is one that I have done myself. I did neglect to put in all the gate pulses you would get from the zero cross ( just r
If you are new to microcontrollers and really would like to have this job done in less than half an hour - go for PICAXE-08M (or any other PICAXE, 08M is 8-pin microcontroller based on PIC12F683) .. Here is an example of 4-20mA tester: ht As this microcontroller can be directly
i'm now implementing a differential amplifer by using AD620. the output of the Ad620 was not equal to zero while the input is null. so i added in a ua741 to null the output. i was wish to use another type of op-amp beside ua741,wat should i use?in order to get better performance. i wan to make my experiment result more various with differet type
If I did really understand what you're talking about is why do you have a symetrical spectral pattern. That's because the Fourier transform give a symetrical spectral pattern but at zero it means that you should have some negative frequencis. Matlab shift all frequencies untill you have just positive ones. So if you don't like this you just need t
Hi, For low power dc control of power triacs you should use an optocoupler such as for example MOC3041 (or similar). This device incorporates a zero-crosing bilateral triac driver. You can refer: Hope it's usefull for you. Good luck.
The easy solution is to use sprintf. It will do the conversion and tell you how many characters it wrote. However, sprintf is big. If you need a small function, check your compiler's library to see if it provides an int-to-string function. If still no luck, someone can probably help you write one. I can think of a couple of ways to compute the n
Big input transistor Try auto zero or chopper technique regards
Hello Everyone, I've started in the VHDL world, mainly because my University is focused on DSPs and microcontrollers. So I've decided to do research in VHDL and FPGAs to encourage research and development in this interesting area. Well, I'm doing digital audio processing in the FGPA (XUP Virtex II-PRO). I found out that using the AC97 codec w
js, Download the Analog Devices AD624 Instrumentation Amplifier (IA) datasheet. It has provisions for trimming both the input and output offset voltages. In your application, the input offset voltage must be much less than the minimum voltage that you want to amplify (10uV). Theoretically, you could trim out the input offset voltage of the AD62
your output load is very small. Assume R1 is close to zero, then the output voltage will hold close to zero too.
Hi everyone, I am having trouble in creating an assembly drawing in P-CAD for my boards. I use my own created library, but when I try to define the assembly layer I cannot use the RefDes attribute (I already used it for the silk and P-CAD will only let me use it once). As I import the netlist for the board in Tango format, the only info I have
I think you can refer to the <> by razavi. it's a collection of papers.:) for less offset, the auto-zero is neccessary.
Your best bet is to contact CDN support. Hi, ncsim: *F,INTERR: INTERNAL ERROR Observed simulation time : 100 NS + 150615038 ----------------------------------------------------------------- Thanks in advance Mahesh Given that the number of DELTAs is a LOT here (150615038) I would imagine a zero
Hello If you meant switching loss of pnp transistor, it is the loss during the transition of the state of transistor. Think your open collector output is high. That means transistor is off (eg collector=5V) and there is no current flow (except small leakage current). So V*I is nearly zeor. Similarly when transistor is activated, there is a curr
ADC's are piplined, flash, delta sigma to name a few. DACs can be r-2r ladder, using auto zero technique, switched cap dacs, capacitive dacs, resistive dacs to name a few. or else could you be more specific on what you want exactly.
yes, dc gain, unity gain frequency and phase margin are different in different loading condition. because the load res will changed the output pole,and the ESR will add a zero,if your regulator have a large output cap,you must simulation the condition of max output current
Dear All, I browsed Hspice manual for .save and .load commands, and tried them. But the commands can only let the simulation skip OP calculation step. Simulation starts from the zero time point again. But I expect it start from the break point. Anyone can tell the details? Thanks Robert
If the current in the resistor is zero, the voltage drop is zero too, so the output goes to +Vcc (In most of the cases 5V). I hope this will help you. I will in the same problem a lot of time ago. (Remember that the oputput is floating, so it takes the voltage you put externally). I hope this will help. Bye and good luck.