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58 Threads found on edaboard.com: 0 13um Technology
I'm designing Low noise amplifier in ADS as part of my project but I'm facing problems during simulation.I went through an earlier thread where you had mentioned about TSMC design kit. Could you please send the design kit of TSMC RF CMOS 0.18 or 0.13um technology. Thank you, Karthik My email ID: karthikselvaam@gmail.com[/e
Hi guys, I'm confused between two vias: nw-to-M1 and rx-to-M1. I figured the first one is from nwell to M1 and the second is from active layer to M1. Looking at two vias in the layout, the only difference is that nw-to-M1 has an extra surrounding nwell compared with rx-to-M1. So if I put rx-to-M1 in a large nwell, is it the same as a nw-to-M1 vi
Hi guys I got a problem in calculating the value of W for my transistor. During the Id-Vgs simulation, I got Id=22uA.This is my parameters Vdd=3.3V Vds=1.65V Vgs=1 Vth=0.546V Un=0.050542 tox=5.141 x 10^-9 eox=3.5 x 10^-17 F/um Cox=3.392 x 10^-12 L=0.56u When I calculate the value of W using saturation formula, it gives me value of
hai guys..can anyone help me?..if i want to design one op amp by using SIL 0.13um (from silterra company) technology in lt spice,how can i do it?..before this,i just use 1um long channel & 50nm short channel for my design where all the parameters are given..does it mean that i have to create my own model text for that SIL 0.13um?..how can i (...)
Hi, i have designed a LNA using cadence 0.13um cmos technology with bandwidth of 4-6 GHz. My dc and sp simulation run well but my pss simulation keep terminating and show me there is an error. Can anyone please help? I have attached the related images104761104762104763 here.
Hi, I wonder could HSPICE give the value of capacitors and inductors that are defined in standard processes such as 0.13um? as you might know in a technology library file for a specific process, electronic elements such as MOSFETs, resistors and also capacitors and inductors are defined by determining their length and width, so for example you can'
Hello guys. I am using UMC 0.13um RF technology to design a TIA. I am facing problems with Assura QRC verification. An error message appears: ERROR (ASSREXT-88016): cap ground signal 'agnd' cannot be found. Check if net 'agnd' exists in design ad has the correct ?netNameSpace (Schematic, Layout) specified in RSF. if the ground signal name c
What are the advantages and disadvantages of the 0.5um and 0.13um technology ?
I am working on design of CMOS second generation current controlled current conveyors (CCCII+). I am working in 0.13um CMOS technology. I am stuck with the design of W/L ratios of the transistors. Can anyone please help me how to design the W/L ratios of the design in this technology. If you have any link that can help me, please post it. If (...)
Hello Everyone, I want to design LNA with below requirements. Can anyone please help in designing LNA? I am using 0.13um technology and Synopsis hspicerf simulator. I am quite beginner so I am not sure where to start and how to proceed. I looked an example in Thomas Lee book and other online but not getting clear idea. Rin = 50 ohm Rout=50
I have used the ideal Gm cell and capacitor to compose a 3rd order chebychev Gm_C low pass filter.The simulation results are as follows: voltage gain=20dB, -1dB BW=10MHz,the steepness of 20MHz is 21dB. But when I design the circuits with TSMC 0.13um technology, using the same Gm and capacitor values and filter structure, voltage gain
Hi everyone, I an new here and this is my first post. I am a newbie to ASIC and as part of my semester project I am implementing a 3TDRAM. I am using 0.13um technology and Cadence Hspice and Spectre tools. I am running into some simulator issues. 1. I initially started in hspice but realised I had to do monte Carlo so i switched to Spectre. But w
hello alll... i m bit new to T-spice.. when i searched for 0.13um technology file from MOSIS, i came to know across such words and whatever file i have downloaded could not worked with my netlist which was generated with tspice 0.18um cmos... can anyone explain why?? what are such things?? thank you..
Hi all, I got a new TSMC .13um kit from MOSIS. But I am having problems accessing them. It has separate technology file(.tf) and the lef files. Because of this I am unable to import the design into the encounter. Its an ARM processor. Has anyone done this before. Could you please guide me as in if I had to write the tech header and layer defini
hi all i am working on a sigma delta modulator using .13um technology and i want an output from the DAC ranging from .225 to 1.575 and my Vdd=1.8 so i can't do that as my common mode input is .9 how can i do this big swing DAC
I design all circuits using TSMC 0.13um CMOS technology and simulate using the BSIM3v3 model with level 49 technology file. I want to use cadence for layout of these, How can I get a pproper libaray of 0.13u technology and work with it.
Iam designing VCO using UMC0.13um technology in cadence .Iam getting the results with pinductor from analog library.But when i replace this inductor with technology inductor simulator showing error "unable to oscillate swing at the output node is very small".can any one explain.Thanks in advance.
Iam using a onchip capacitance of 50pF as a coupling capacitance.a 100umX100um giving 10pF capacitance.iam using five capacitos of 10pF each in parallel.can i place these capacitors one over the other.if it is so maximum how many capacitors placed one over other.iam using 0.13um technology.pls explain.thanks in advance
Transistor length depends on the technology. 45nm, 65nm, 90nm, 0.13um,..... it varies.
Hi, I am drawing the layout for my design using IBM 0.13um CMOS technology (virtouso). This is my first time using the IBM process so I have a few questions about the layout drawing. 1/ what is the different between pin and pad? When I insert input and output pins in my layout, the LVS can recognize them as IO Ports. 2/ Are the pads requi