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12 Threads found on edaboard.com: 12bit Sar
The sar-12bit may be configured as a DAC but considering the learning curve will have just to make 2 sine waves and the chip capability, I can think of better choices and more suitable applications for the chip when you learn how to use it. A protoboard is not the best for low noise sine waves with long wires. It seems you need to learn how a
MCU as STM32F303 allows you to connect two ADC in dual mode. Two 12bit 5MSMPS work as a ONE 10Msps Unfortunately, no one does, how to solve Front-End Amplifier for ADC in dula mode. Use one amp for both ADC or two for each ADC own amplifier?
Pipeline will be very difficult to achieve 12bit and even more difficult for 14 bit, because of noise reasons. According to me, don't even consider it. Sigma-delta is perhaps the way to go. But you need the appropriate technology to achieve the frequency you want, up to a certain value. With fast technology, maybe even sar will do the job. BTW, fla
As you can see the structure, it's a 8it sar ADC, we just replace the capacitor array with split capacitor array to realize a 12bit 1K sampling rate sar ADC. Its designed for EEG singal processing which has very low frequency. Now we have builted an ideal model in cadence and use ideal DAC to convert the ADC output. We measured the THD (...)
Guys, I need to design 12bit 1MSps sar ADC with input having of 0~VDD range and 20KHz. Input will be coming from selection MUX. Can single-ended topology cover for this spec or should go with fully differential topology? And if I pick fully differential topology, I need to single-to-differential converting for ADC input. Then it will be tough t
HI, All: The project is a 12bit sar-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider. In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the m
For kHz, just use a sar topology. It is suitable for 8-12bit resolution. Bastos
HI ALL: I have a sar adc 12bit 200ks/s get resolution of 12 bit, so the comparator of sar adc its gain need 20*log4096=72db ,and to have sample rate=200ks/s, the clock need to set 12*200ks/s=2.4Ms/s. And there is a question, if the comparator is used opamp, is there a circuit about gain=72db at it correct
Hello, next time I will take part on some 12bit sar ADC workshop. I'm an newcomer on this ADCs, I know only coarse how they works. And I want ask some interesting questions! Can somebody help me? Thanks
I am currently working on a low speed sar ADC(around 10KHz sample rate) is it possible to get a 12bit resolution with 6bit(from resistors) + 6bit (from capacitors)? i know it's possible to get 10bit from poly resistors, but not so sure about capacitors.
it is diffcult to get 12bit. you can search some paper about "error average" or "digital calibration"
sar ADC may be more suitable no sar R2R only for 8bit ( resistor /switch mismatch issue) Cap charge share -> 10bit if sar use > 12bit use R_string + Cap for low freq < 1K I think you can use dual slow or delta_sigma