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138 Threads found on 200 Mhz
Please calculate what is the impedance of a 10pf cap at 200 mhz, so you realize how preposterous the requirements are.
I would like to know who produces magnetics for frequencies over 200 mhz. I have heard even about ferite for 4 GHz. How can I get information on permeability and tan(delta)?
I am trying simulate a ferrite core antenna and coil integrated. but I do not have idea by where start. please can you hel me? I need know how simulate with CST the ferrite material or how called or I have that create a new material with its own characteristic. The antenna start up 20 to 200 mhz.
Hello, I need help with my project. Itīs about A-scan ultrasound, used for eye biometry(more here: ). It will serve as a learning tool at my school. I want to get signal from ADC to PC: ADC -> buffer -> ATXmega -> USB -> PC or ADC -> parallel-to-USB converter -> PC FPGAs are common
The VHDL code will surely generate an 1% duty cycle pulse (not a legal servo pulse width, I presume) with fclk/1000001. In case of a 50 mhz clock, a 200 ?s pulse with about 50 Hz repetition. By using an unregistered comparator, the output will have some glitches, you may want to correct it. No idea how you managed to get no output in your te
hi my friend, i have question,what PCB we should use in frequency 150 till 200 mhz; in 400mhz too;
Hello everyone, I designed a Time-to-Digital Converter (TDC) configured by CARRY4 primitive in Virtex-5 (XC5VLX50T) FPGA using ISE 14.7 and Isim as the simulatior for Post place and route simulation purpose. As you see, in the attached figure, my "clk_in" signal is 200 mhz fed to the DCM and the "output_test_point" is the output 2X of DCM t
I am designing meander antenna in ADS for f0=95mhz. I would like to know how to define the coplanar waveguide (CPW) port for structure. Also for solver setup if i m simulating my structure from 50 to 200 mhz range then what should be the appropriate mesh frequency and number of segments per wavelength. Also the value of Nmax in frequency (...)
Dear all, I am limited to this microcontroller: MSP430I2020. It has 16mhz clock, 16bit timer. I need it for controlling a switch at a frequency of 200KHz, probably in this case I will have around 1% Duty cycle step and I need at least 0.01%. Does anyone have a solution? Thanks in advance.
A diode in series with a capacitor cancels the diode current. Operating a 200 mhz OP without any bypass capacitors is really a bad idea. Generally you'll start verification of circuit by measuring all DC levels (e.g. against common ground) with a multimeter.
hi; i have 10 mhz bandwidth in 200-210 mhz and i want to convert it to digital with 20msps and 10 bit resolution. any way i wanna know shall i down convert the signal to 0-10 mhz or can i down convert it to 50-60 mhz and sample it with 20msps adc?? ( there is some problem with adc (dc problem and (...)
check the datasheet here the IF frequency is 0.1-800mhz. but it misses that how much BW of this frequency the upconverter can bear. for example, My IF is 200-800mhz and any LO, it will upconvert it????????? it 600mhz BW
What exactly do you mean by "total delay"? the timing report indicates that if you provide a 200 mhz clock, it should all work without timing related problems.
I need to design an amplifier with gain greater than 10 and bandwidth from 200 kHz to 2 mhz using an 2n2222 transistor. Please help.
Hi, I have designed an opamp of gain 120dB and ugb in the range of 2-3 mhz with power consumption nearly 0.5 mw and settling time is in the range of 200 ns with a single power supply of 1.2V. I have a query that which area needed such an opamp specification........ I have read papers on high gain low power opamp but my query is still unsolved.
I am designing a time interleaved at 800mhz. The interleaving factor is 4. Therefore each sub-ADC should work at 200 mhz. Input frequency is 200mhz. Now the question is to find SNDR of the sub-ADC at 200mhz. The problem is if I apply this frequency i would get a dc (...)
For 32 bit bus running on 200 mhz clock, Bandwidth=200*32=6400 megabits bits per second or 6.4 Gbps.Throughput= actual data rate obtained during normal operation. throughput <= bandwidth
A 32 bit data is coming at 100 mhz continuously. This data needs to be read at 200 mhz with data width of 16. Please design a digital circuit for it. Regards
I want to make a perfect 100 kHz pulse with 50 % duty cycle. If a perfect 200kHz pulse can be generated, I know how to make it 100 kHz perfect 50 % duty cycle with flip flop. So I want the best solution to make a 200 kHz pulse generator. Does 555 timer (bipolar one) make a perfect 200 kHz pulse? In the datasheet I didnot find any specs
Hi, I should simulate a Twisted pair using low voltage differential signal. I know this parameters for the signal: Trise=tfall= 1.2 ns Working at 200 mb/s Which is the frequency in mhz?25mhz?