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## 2nd Order Sigma |

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2nd order sigma delta , 2nd order , 2nd order filter , 2nd order butterworth filter

2nd order sigma delta , 2nd order , 2nd order filter , 2nd order butterworth filter

64 Threads found on edaboard.com: **2nd Order Sigma**

Hello everybody! Recently I have designed a **2nd** **order** Incremental **sigma**-Delta ADC. I have two main concerns about my design:
1 - The goal was achieving at least 14 bits, but unfortunately after realizing the FFT in **order** to obtain the outuput spectrum, the fundamental is attenuated by 20 dB. I don't know which reasons can (...)

Analog Circuit Design :: 10-15-2015 14:04 :: mark4444 :: Replies: **5** :: Views: **914**

I am creating a second **order** delta **sigma** modulator for a fractional n pll.
First I created the first **order** one. It worked ok when I removed the output flip flop that had to act as a comparator. Of course there's some sort of comparator glue logic. However it is combinational circuit. I wrote a code in matlab and it worked fine, designed the (...)

Analog Circuit Design :: 05-02-2015 16:17 :: Debdut :: Replies: **0** :: Views: **1054**

Hi~~Everybody,
Recently, I have designed a second-**order** **sigma**-delta modulator using the CIFB architecture.
The fin = 1KHz, fs = 1MHz, and Vin = 1V.
In the first, I use the Matlab to simulate its function. The output spectrum shows that the noise floor at dc frequency is about -120dB.
But when I use the actual devices of the OPA, t

Analog Circuit Design :: 02-13-2015 06:03 :: davison7 :: Replies: **2** :: Views: **823**

This Source degeneration Gm-cell with negative-impedance-compensation(NIC) technique is used to
design loop-filter for **2nd** **order** **sigma** Delta ADC. I dont know what are the parameters/specifications needed for the design of the ADC. Also i need input parameter values like Vsin, Vref, Vss for this Source-degeneration Gm-cell. I am using (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-16-2014 06:17 :: babu1sharath :: Replies: **0** :: Views: **626**

I have an ideal **2nd** **order** 1-bit (OSR=2048) **sigma** delta modulator. The SNR of its output is 145dB
Unlikely.
How do you determine SNR? My SD books don't grant 145 dB SNR for **2nd** **order** and OSR 2048.
If the ADC had this SNR, it won't reproduced by 19 bit output length.

Digital Signal Processing :: 11-22-2013 09:19 :: FvM :: Replies: **6** :: Views: **1212**

my **2nd** **order** DSM simulink model:
I would like to ask how can i get the PSD of DSM like this?
Thank you for your help

Digital communication :: 11-07-2013 05:39 :: pakyin :: Replies: **0** :: Views: **665**

See a left block diagram in attached first figure.
This is a simple **2nd**-**order** continuous time delta-**sigma** ADC of Feedback structure with a feedback path for excessive loop delay compensation.
This compensation path is implemented by DAC3.
In this block diagram, I assume passive summation before quantizer. So gain K is required before (...)

Analog Circuit Design :: 07-16-2013 12:24 :: pancho_hideboo :: Replies: **0** :: Views: **679**

hello All ,
I have a problem of getting the PSD plot of **2nd** **order** switched cap **sigma** delta
the opamps, switches are designed using veriloga.
the input is taken every 0.1s using a reset switch on the9242792428 integration cap (incremental ADC)
vref= +-0.5 , vin=+-.216 (DC input)
OSR = fs/2fo
f

Analog Circuit Design :: 06-16-2013 11:54 :: ali kotb :: Replies: **0** :: Views: **588**

hi all,
first ,i put the design of **2nd** **order** **sigma** delta ADC on matlab (simulink) to make high level design and now i want to know how can i get SNR from Simulink model (how to plot SNR).
actually, i have an idea that i can get output data from simulink and get SNR in Workspace with equations of schreier toolbox, but i don't know how can i (...)

Analog Circuit Design :: 01-29-2013 13:47 :: Ezzooo :: Replies: **0** :: Views: **663**

Hi,
I need verilog code for **2nd** **order** digital delta **sigma** modulator.
any help would be appreciated.
Thanks,
Sree

Analog Circuit Design :: 10-17-2012 18:07 :: sreechan :: Replies: **1** :: Views: **1147**

Regard to everyone,
Here is the problem:
Currently I design a **2nd** **order**, delta **sigma** modulator with CIFF architecture using Schreirer's Delta **sigma** Toolbox for matlab, and there is one thing that confuses me. When I get scaled coefficients which provide satisfactory NTF and simulate architecture with Simlink, input of (...)

Analog Circuit Design :: 07-27-2012 00:20 :: ser.rif :: Replies: **0** :: Views: **1291**

Hy moylando,
I am interested on this instability issue of SD modulators. I am having the same problem for a **2nd**-**order** continuous-time modulator, however for higher amplitudes (-3dBFS). I am also using the same DC gain and constant time for both integrators. Anyone could provide some comments on this?

Analog Circuit Design :: 07-16-2012 13:16 :: uroddy :: Replies: **2** :: Views: **801**

Hi all, I am working on a **sigma** delta adc which should give **2nd** **order** noise shaping (40dB per Decade), but i only see 1st **order** noise shaping(20dB per Decade). Any pointers as to where might the problem lie? I am working in current mode continous time domain.

Analog Circuit Design :: 03-19-2012 16:28 :: engrMunna :: Replies: **0** :: Views: **780**

Good day everyone,
I am Patrick. I am an undergraduate student taking my thesis. My group's topic is about the **2nd** **order** **sigma** delta modulator. My task for this group is to design the digital far as I know, The purpose of the digital filter is to remove the quantization noise that has been pushed to the higher frequency.Thus, improving

Analog Circuit Design :: 01-21-2012 02:39 :: symphonics :: Replies: **0** :: Views: **658**

Digital Signal Processing :: 12-09-2011 15:25 :: singhji0000 :: Replies: **0** :: Views: **797**

In the **2nd** **order** **sigma** delta (mesh architecture) document "ROBERT AND DEVAL: SECOND-**order** INCREMENTAL A/D CONVERTER" , up-down counter approach to implement filter section (page 738 and 739)
the filter stage1 after comparator 1 uses x = x + xx * (n - i +1)
where xx is comp1 output and x is output of filter and 1*
*

Analog Circuit Design :: 12-08-2011 13:00 :: singhji0000 :: Replies: **0** :: Views: **792**

hi all
im doing my proj sig del CT
fs=6.144Mhz
signal bandwidth is 24000 Hz
**order** 2
Nrz pulse feedback 1 bit quantizer
im implemnting ota in 180 nm tech
vdd=1.8
vss=0
i designed the ota for input common mode at 0.9v
wat shud be the input given for the modulator.
A sin wave with .9 dc and some ac on it ?
0r
A sin

Analog Circuit Design :: 11-28-2011 13:27 :: satyanitt :: Replies: **0** :: Views: **658**

Hi,
I designed **2nd** **order** **sigma**-delta modulator (1bit), and made chip, and measuring now.
I use FPGA after modulator output. the FPGA is used for sinc3 decimation filter (16bit out).
I have a distortion problem for measurement.
test condition;
VDD=3V, VSS=0V, VREF+=3V, VREF-=0V, VCOM=0.4*VDD(from external)
fclk=100k, 250k, 500k (...)

Analog Circuit Design :: 11-11-2011 02:55 :: you23 :: Replies: **0** :: Views: **550**

Hi, I am working on design of single loop **sigma** delta modulator and for that I am using **2nd** **order** CIFB architecture. My question is do we need to have gain stage before delayed integrator in this structure? I did put two gain stage b4 each of the integrator because I was not getting proper output at each integrator output(which according to (...)

Analog Circuit Design :: 10-20-2011 21:06 :: nish_2511 :: Replies: **0** :: Views: **575**

designing a **sigma** delta **2nd** **order**...CIFF architecture....
in literatures they hav suggested to use more linear and low noise first integrator for better they said first integrator is a power hungry one...
bt where the difference in design of low noise cum low power OTA and other OTAs lies... both integrators power is det

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-14-2011 06:59 :: satyanitt :: Replies: **1** :: Views: **970**

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