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73 Threads found on edaboard.com: 6 Layer Stack Up
Hello, all the overlaps on tStop layer are marked up and listed when I'm doing the DRC, which is quite annoying and inconvenient. How can I stop eagle from listing them as errors? This is what it looks like: 146294
There are many GND Vias between RF traces, but In the middle of the GND plane, some vias each have a black square(copper removed) next to it. 135956 What's the reason behind this design? We are considering follow the EVB's design in our project. Any help will be greatly appreciated!
i don't how to matching 100 ohm and 50 ohm impedance in 2 layer pcb , i need trace width and spacing pls any one can help me..
Hello. I have a more or less complete design for a lab supply which I have been trying to implement on a 4-layer PCB, even if changes may occur this thread wont loose any value for my progress since they will if any minor. Here is a muck-up of the design to be the subject here: 116719 This is my first such a comple
HI all, I'm designing a multilayer PCB (12 layer ) and I decided to use layer 5 and 6 for power distribution. So the question is can I put one voltage(eg. 1V) on one plane(eg. L5) and then a second voltage(eg. 3.3V) on other plane(eg. L6) on top of it? OR i have to have GND plane In-between? layer L4 and L7 are GND (...)
I am beginner in the Altium, and need guidance on how to proceed with the schematic and pcb layout mainly. The board will keep all the components welded on one side only. The other side will need to be free to be engaged in an LCD. I have many doubts, did just a basic course to know and use the basic tools available in Altium. It will be very diff
Hi, I am new to rf design. I'm trying to design a 4 layer PCB. the stack-up looks like this: 1.GND 2.Power 3.signal 4.GND the data rate in layer 3 (signal layer) is about 16 GHz. What do I have to consider? I mean, what is the best method (draw finite GNDs? vias between layer 1 and 4?) in ADS (...)
I am printing a 2-page fabrication drawing: Page one is the board/drill guide, and page two is just the fab notes and stack-up. The board outline is printed on both pages , even though my "board outline" mechanical layer isn't one of the layers selected to print for page 2. Is there a way to turn that off for? Thanks!
Hello, I wanted to place a stackup legend on my design files. It puts a nice bracket, it names the layers aaand.. that's about it. Details are filled in in the layer manager (obviously) and I enabled all options when I 'tabbed' after placing first corner. Seems I did just about everything as mentioned in (...)
I'm looking for stack up recommendations (keeping in mind readily available materials) for a 6 layer board I'm working on. Design requirements dictate the following: - maximum 6 layers - lots of high speed traces DDR3, SERDES, Gbit ETH, USB2.0 etc - high speed signals due to BGA need to be 4mils wide So for 50/100Ohm with 4mil (...)
Hi Folks, I'm using Orcad Layout (v9) to route my PCB (2 layers , top and bottom only). I need to achieve the following requirement, On Top layer i have to manually route important traces. Auto Route rest of the traces on the bottom layer. (No more traces on top) How to achieve this ? I route manually important tr
I need +Power, -Power, 2 routing layers, and a ground plane. However, I don't know how to choose my stack-up? If someone could explain all the different possibilities along with the trade-offs I'd really appreciate it. I'm concerned with things such as cost and routing difficulty and EMI and all that good stuff. ALSO: what are the disadvantage
Hi Cadstar have really nice layer stack editor but i still not find a way to put that info into the gerber or documetation drawing ? still have solution to make it by hand and put it on templace but i sure zuken not put lot of tome for make great layer stack up editor and forgot way to put it on output file (...)
Can any body help me How to decide layer stack up in Multi layer designing?
Hi everyone, in my design has BGA(256pins),DC-DC converter,opto isolator,schmitt trigger,connector is avaiable and power and ground are 1.5V(1.5A),3.3V(2A),5V(1A),+15V_FTR,+15V_DC,5VDC,+ 5V_FTR,+24V_ISO,ISO_GND,GND,AGND,minimum pitch details for package tssop package-0.65mm,soic-1.27mm,BGA Pitch-1mm i am planning to design in 6 layer ,Here
Hi , I am designing 24 layer card with 1GHz having 12 BGAs , Is there any guideline for layer stack up for BGA Thanks Ashwin
hi robis, top layer and bottom layer is signal layer if want to design 2 layer top and bottom is enough no need to assign extra layer like ground or power (planes). usually layer are assign in multiplication of 2 like 2 layer,4 layer, 6 (...)
I went through the Si self teach guide, over a period of time, started at page one and did everything in the guide in order, that is the best way, its quite a steep learning curve, but can be donein a couple of weeks. I cant think of any easier way, to use the software properly requires the proper training, there is no simplistic path to getting r
Hi all, Engineers who are familiar with HyperLynx please help solve stackup problem in HyperLynx. I'm getting stackup problems message when trying to simulate a one single net in my PCB. My PCB board has 2 physically layer only. But when trying to simulate a got warning message "The stackup has error". And when I opened (...)
Hi everyone, I was wondering which tool is best for model PCB stack up and able to do simulation on the model. We are talking about multiple layer. I would like to be able to change the dielectric constant and dissipate factor for core a on each layer. An example of layout is: Plane Gnd Core Signal Cu pre-preg plane Gnd I (...)