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Adc Noise Cadence

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ADC Value gets changed when a Digital output enables

electrical noise may lead adc value

About can't find PDK in layout in Cadence

I have a VCVS instance in my schematic design. I can't find VCVS in layout after generate from schematic because there is no VCVS PDK in Layout. How can solve this problem? Thanks. Attached is VCVS symbol in schematic.

Finding W and L of transistors from DC operating point.

Hi guys, I have a schematic of OTA amplifier: 157362 I want to know the W and L that were used to design this OTA. I don't have more information other than the ones provided in this picture. since all transistors are in saturation, I thought about using the saturation current equation to find (W/L) ratio. by assuming

Easiest way to get 5v and ~1V

Hi, A battery voltage varies....and the same magnitude in % your sensor signal will vary, too. --> high error. You want it simple... Sadly you don't give much information about the whole application. Especially: where does the Opamp output signal go to? If to an adc: Then I'd modify the circuit a little bit. I'd use a voltage divider fr

Reducing RAM & ROM consumption in coding

How can I rewrite this code to use less RAM & ROM? adc: 10bit. Speed: 1MSPS. Data input range: 0-5V. CPU: DSPIC30F2010; 16bit. This code is working fine. But consuming 25% of total ROM & 40% RAM. I need suggestion to rewrite this code so that I can save some RAM & ROM. I need at-least 20 samples to get the best result. Signal is both AC & D

FIR Filter general question

So, I transform the coefficient in integer value of max 17 bit (1 bit for sign) Why not simply treat the signal as 18 bit signed? If your original adc signal is 16 bit, you'll use 16 rather than 18 bit signed. Similarly, the coefficient resolution will be demanded by the filter transfer function accuracy, not the multiplier width. A

problem with ADS license

Hello everyone! I want to simulate the schematic in ADS, but the problem occurs when I change a new designkit. While, I can simulate succesfully by using another designkit. Does someone know te reason? Thanks a lot157347

The magical audio filter other opamps?

Hi I have found this filter/amp combination, being simple with nice features. I wonder can I use other opamps like the ne5534 or is the performance specific to the 741 and will differ if using other opamps? Also how about Jfet based ones like the tl071?

Intermediate Frequency for I and Q components

I am working with gnss sdr software for processing rf signal captured in file. In gnss sdr software configuration the data source mentions adc sampling rate and type as i and q samples. Nothing is mentioned about IF frequency. Does that mean the intermediate frequency is always zero for I and Q components?

Resistor at input to high side current monitor IC

Hi, Should resistor RP on page 1 of the HV7802 datasheet ideally be equal to the value of RA? HV7802 datasheet

Measuging signals with dsPIC30F2010

How can I measure the average points of the peak if these signals and one avg of max&min value of sine wave. Note that I'm new with dsPIC ics but have been working with PIC and atmel ICs for a long time. Yes, I can do it in my older method but those are time consuming for this product. That is why I'm asking for suggestion from experienced friends

indivisual out different from differential output in fully differential amplifier

Hello, attached is the transient pic of the fully differential amplifier I have designed, if you look to the vo+ and vo- you will see the sparks on it, however the differential coltage is clear due to the subtraction, my question, should I be concirned about the individual outputs or only have to look to the differential output (Vo_diff)

Incisive Intallation using Installscape

Hello, Want to install Incisive add on to cadence DFII using Installscape on Centos 6. Do I tell Installscape where DFII installation is already and then install Incisive ? Does Incisive have to be installed before cadence DFII or can it be installed after the cadence installation ? Any special considerations for Centos ? Will (...)

Step Down 16khz noise output on VIN

Hi, I'm using a TPS54528 voltage regulator to get an 1.05V output, the input is 5V. However once I apply some load (eg. 1.5 Ampere) I get a 16khz spike on VIN (the closer I go to the chip pin the bigger the spike will be). So since it's 16khz it will result in a high noise, and since some other regulators are also attached to the 5V rail the

Becoming PCB Designer

Hi all, I am an Engineering Technician, I have been soldering and de-soldering in years. I have designed and home-made toner transfer PCB as well. Now I am thinking to take course for professional PCB design for my career. I am wondering which courses I should take. Did anyone take this course, is it good for beginners? Or any recommendation?

Noise and variability analysis for differential amplifier in cadence

I have a theoretical understanding of the effect of noise from different transistor and variations in different transistor. I want to know how to simulate in cadence. For for the differential amplifier - 1. Theoretically noise is done individually for each transistor and then added up. The final value will be in noise (...)

P1500 Wrapper implementation

Hi, I am new in this field. I have rtl code of an IP. Now I want to implement wrappers around the i/o ports. Can you please suggest me how to do that? Do i need to write rtl code for the wrappers as well or any other means are available? Thanks in advance.

Heterodyne detection, non-linear mixer and minimum detectable signal (2-way radar)

I've been working on a transceiver system with BGT24LTR11 chips at it's core and I was unable to achieve necessary signal to noise ratio. I want to know whether it's theoretically possible and for that I need to understand how the terms in the title all intertwined. The following parameters/figure of merit I'm familiar with: Minimum detectable

PLL LPF causing an odd short

Hello all, 157237 I am having a problem I can't seem to diagnose: I have a PLL centered around a ~24 GHz VCO. The block diagram is shown above, defiantly not the best design, open to criticism. The VCO provides a N/16 output which is mixed with a 1.

High Voltage Resistor divider

I can't see why noise should be a problem in the design although a full schematic of the sensing circuits would be useful. An LPF should suffice, other than that I think the next best solution would be to S&H when the pulse is present before measuring. I suspect the issue is the high impedance at the potential divider but dropping the resistors va