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32 Threads found on edaboard.com: **Adc Snr Fft**

Hi, I have designed an **adc** in cadence virtuoso and i want to calculate the metrics such as **snr**,SINAD,ENOB etc. For example i want to calculate ENOB. I read everywhere that i need to do an **fft** my input, or simply use the spectrumMeas function. So i am using a sinuid input of 875MHz as fin and 2GHz as flck. In the field in spectrumMeas i use (...)

Analog Circuit Design :: 10-27-2016 04:27 :: Pavlanto :: Replies: **0** :: Views: **642**

hello
i was simulating of a first order **adc** using code given in book of richard scherier. for calculating **snr** he uses (page 265)
**snr** = calculate**snr**(spec(1:ceil(N**fft**/(2*OSR))+1), tone_bin)...
where spec is spec = **fft**(v.*ds_hann(N**fft**))/(N**fft***(nLev-1)/4); (...)

Digital Signal Processing :: 12-05-2014 06:05 :: sona_ :: Replies: **1** :: Views: **937**

Hi, there!
Recently I am testing an 8b **adc** and get the **fft** results. Then I can find the **snr** and SFDR as usual. But I find the HD2 of some chips is higher than HD3, the left is not. And sometimes the HD2 is larger more than 15dB than HD3, but part of them are close to HD3. So I want to know what does it mean?
Are there materials about (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-25-2013 16:11 :: urian :: Replies: **7** :: Views: **1458**

hello Eminent.Engineer,
I hve also designed a delta sigma **adc** and i calculate the **snr** order to caculate the **snr** after the modulator you must make the fast fourier transform function (**fft**) by MATLAB after the modulator.
About the decimation,until now i have designed the complete **adc** in Smulink (MATLAB) (...)

Digital Signal Processing :: 04-01-2013 16:48 :: fasto2008 :: Replies: **4** :: Views: **2575**

method 2 is one i have used before. i set the dac to have 2 bits mode resolution than **adc**.

Analog Circuit Design :: 12-26-2011 08:27 :: steadymind :: Replies: **1** :: Views: **628**

hi folks.
i am trying to test the 10 bit pipelined **adc** schematic i designed. The procedure i am following for finding the SNDR is " take a sinusoidal input signal nearer to full scale range.Using an ideal DAC reconstruct the signal. Plot its **fft** ,say for 1024 points,take those values and find SNDR, THD, SFDR , **snr** from matlab by giving (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-14-2011 05:36 :: chandra3789 :: Replies: **1** :: Views: **1066**

hi, all,
i design a **adc**, and now it is tested, but i have no any software to get **snr** and THD+N THD..., but some digital data is sampled from a logic analysis device, and a piece of MATLAB procedure is need to get **snr**, THD+N, THD and the **fft** figure, but i can't compile the procedue.
can you upload the procedure the (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-24-2011 12:38 :: huangjw :: Replies: **0** :: Views: **939**

hiiiiiiii
I'm working on sigma Delta **adc**
CAN ANY1 PLEASE HELP ME ON WORKING WITH CADENCE SPECTRE FOR **snr** CALCULATION
HOW MANY CYCLES I SHOULD RUN THE TRANSIENT ANALYSIS??
IN ORDER TO CALCULATE **snr**
PLEASE HELP ME IN FIGURING OUT THESE VALUES...
how to come to conclusion to **fft** fundamental frequency of input (...)

Analog Circuit Design :: 02-07-2011 17:06 :: kapil411 :: Replies: **3** :: Views: **4212**

I remember calculating SFDR for 100 Mhz **adc**. I see if I can find the C code for it and extrapolate equation and post it here. That might help you on the **snr**.

Digital Signal Processing :: 09-05-2010 02:15 :: eziggurat :: Replies: **3** :: Views: **3557**

I have tried to estimate the **snr** of the sigma delta conversion after the sinc^3 filter and got lots of noise at the low frequency end. It looks like the opposite of noise shaping, see attached. When **fft** of the bitstream is plot the **snr** is almost twice as high for the same frequency. Am I using the sampling rate a lot higher than the signal I (...)

Analog Circuit Design :: 04-19-2010 21:45 :: ElEngineer :: Replies: **1** :: Views: **1994**

Dear All,
In N-**adc**s why we need to follow coherent sampling method for calculating **snr**.
Bye.

Analog Circuit Design :: 11-01-2009 14:19 :: coolstuff07 :: Replies: **2** :: Views: **1790**

Hi guys,
I am currently designing a column parallel single slope **adc** for a CMOS image sensor.
I have done the DC, AC and Transient analysis. I am aware that I need to do .**fft** to determine the **snr** and ENOB.
Are there any other simulations that I may have missed? Appreciate all the help I can get. Thank you all!
hyuuga_patik

Analog Circuit Design :: 07-16-2009 02:15 :: hyuugapatik :: Replies: **2** :: Views: **1496**

ideal **adc** + actual DAC
the input signal is sine wave
then **fft** the output signal of the DAC

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-07-2009 08:10 :: lwjbh :: Replies: **2** :: Views: **1695**

Hi all
I use the HSPICE to simulate the whole pipeline **adc**.
I want to check its **snr**. So i run the tran. simulation with 2048 points, then transfer the .tr0 file to matlab to **fft** to get the **snr** value.
If i use 0.01ns transient step in tran simulation, the **fft** results is about more 60db (My (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-23-2008 04:28 :: gdhp :: Replies: **3** :: Views: **1616**

HI...
I AM PRASADH, I AM DOING MY PROJECT ON FLASH **adc** IN CADENCE..
HOW CAN I DO THE **fft** ANALYSIS IN CADENCE SPECTRE FOR MY CIRCUIT..
ACTUALLY I HAVE TO MEASUER SFDR,SNDR FOR MY CIRCUIT .
CAN ANYONE HELP ME PLEASE....
THANK YOU

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-07-2008 09:53 :: prasadel06 :: Replies: **5** :: Views: **2252**

Hi, I have some question regarding the script I got. Part of it is as follows:
.
.
.
% Create the minimum, 4-term Blackman-Harris window for **fft**
pwr_win=0;
for i=1:Nt %where Nt is the no. of **fft** bins
window(1,i)=0.35875-0.48829*cos(2*pi*(i-1)/Nt)+0.14128*cos(4*pi*(i-1)/Nt)-0.01168*cos(6*pi*(i-1)/Nt);
p

Analog Circuit Design :: 03-18-2008 01:19 :: pseudockb :: Replies: **0** :: Views: **1632**

HI all
i am simulation a pipeline **adc**. I give a sine input, and do .tran simulation in hspice.
Then catch the 10-bit digital code to do **fft** in matlab.
Then i want to know, the **fft** results can give the **snr** results? And is the noise compont
included in the tran simulation results?
What performance of (...)

Analog Circuit Design :: 01-09-2008 03:24 :: gdhp :: Replies: **3** :: Views: **3393**

You should place an ideal DAC after **adc** (DUT) to get the analog output and simulate what you need :)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-19-2007 12:24 :: Alex_IC :: Replies: **5** :: Views: **1211**

for calculating the SFDR for an **adc** .
coudl u please tell me the origin of this spurious signal ..
in **adc**

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-03-2007 08:23 :: manissri :: Replies: **1** :: Views: **1103**

Hi, I am working on sigma delta modulator based **adc**.
I have output bitstream from the modulator and would like to measure **snr** and SNDR using **fft**.
How could I possibly separate the signal and noise from the output of modulator?
Also, is there anyway to separate the noise and distortion from the total noise from the modulator output (...)

Digital Signal Processing :: 07-26-2007 21:41 :: sehun1119 :: Replies: **3** :: Views: **1587**

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lna circuits | current source pwm | generate timing | resonators | lcr and meter | bpsk mod | mode matching | voltage change detector | xilinx cable | clamp circuit