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123 Threads found on Ade Spectre
Linux MINT is not supported platform for Cadence ade.Cadence ade 6.17 supports Redhat and Ubuntu Linux distros.I have installed on a CentOS 6.8 and I had faced to resolve many compatibility problems. Ubuntu is free and supported, why don't you try it ??
does any body know any way for doing it in cadence.What do you mean by "cadence" ? This thread title refers "spectre". So simply invoke montecarlo analysis of Cadence spectre. See "spectre -h montercarlo". If you use Cadence spectre in (...)
Hi, I work with cadence and I use GoldenGate instead spectre for simulation. And I want to display the simulations results in the ads data display window to can write equations in the display window. But I can't open ads data display window from the Cadence Analog Design Environment ade. So, my question how to open or (...)
Cadence ade is not a simulator. You can launch various simulators on ade. What simulator do you use. Show me simulator name with correct terminology and its version.
u mean stimuli...??"input.scs" is a spectre Netlist when you run spectre from Cadence ade. I think you use device model files of HSPICE Format for Cadence spectre Netlist. Use device model files of spectre Format. Or add "simulator lang=spice" at top of all device (...)
how are u doing corner analysis ? using cadence ade XL ?
There is no tool whose name is cadence. Even if you use Cadence ade, we can use various vendor's simulators such as Synopsys HSPICE, Mentor Eldo, Keysight ADS, Keysight GoldenGate, Cadence spectre, etc. Always describe correct tool's name and vendor's name which you use as tool or simulator.
I set the gain of vcvs in Hspice simulation from the ade, but the netlist is: e1 s2 0 vcvs s1 0 1, so the gain in this netlist is 1, not 2. the right answer should be: e1 s2 0 vcvs s1 0 2. Also, the set the delay of vcvs, in Hpsice netlist, the delay will not present. When I switched to spectre in ade, it is ok. Do you (...)
I followed this tutorial to set the FreePDK15 up : put due to running spectre this error occurs : Error found by spectre during circuit read-in. Error found by spectre during circuit read-in. ERROR (SFE-1138): "/home/mohammed-turki/pdk15/cdslib/FreeP
Hi All, I have encountered some problem about errors in ocean script sim for PVT. FYI, at certain condition of PVT, Ocean sim completed with errors, however, when I manually re-run the same condition using ade, the simulation is able to completed successfully. Any idea what may be the causes is? Thank you
Hello, I created a layout of a not gate using Virtuoso Cadence layout tool. Then I did the drc check and fixed all errors and I extracted the layout. After that I went into the extracted layout to try to post simulate it using ade L (spectre) after setting up the Analysis and the outputs and the stimulus. However I am getting this (...)
When running stb analysis, I would like to see the bode response not just for the entire loop but for some intermediate nodes to figure out how much gain/phase each stage in the loop is giving me. I have not been able to find how to do this in Cadence ade.
Quote from previous thread: I am trying to run simulation in Virtuoso ade GXL. I am getting the following error. "adeXL-1613: Following tests use older version of spectre. Make sure to use MMSIM60 or above for these tests." We have installed MMSIM62. but the above problem is still th
You need to mention the target technology to get specific answer.You can simulate the MOSFET in Virtuoso ade using spectre Simulator and observe the Vth value in the Result Browser.
Dear All: In IC 5.1.41, I create a cell which contains a pmos with length = pPar("Pl") (use passing parameter). In ade, I generate the netlist for spectre through simulation -> Netlist -> Create The generated netlist is wrong: M0 (A CKB B IVDD) pch3 l=Pl w=3u m=1 nf=1 sd=540.0n ad=1.44e-12 \ as=1.44e-12 pd=6.96u ps=6.96u n
Hi, I am trying to do post layout simulations of a circuit in Virtuoso ade-L using ELDO. The layout extracted netlist was generated using Starrcxt tool. Now how can add this extracted netlist in ade to get post layout simulation results? regards
Hi everyone! I'm trying to simulate a simple voltage amplifier made using models from AMS Hit Kit 4.10 (ams 0.35 um) in Cadence IC When I try to simulate the circuit using ade L and spectre as simulator I got this error in the Output log menu. (See attachments) 111717 Where MP and MN are pmos4 and nmos4 from
Hi guys, I was wandering if anyone has ever dealt with history file of ade XL of Virtuoso by Cadence. These files are stored in the folder //adexl/test_states///spectre/ I wanted to add another history file from another view of the same cell, so I just copied at the new history file in the (...)
Hi guys, I was wandering if anyone has ever dealt with history file of ade XL of Virtuoso by Cadence. This files are stored in the folder //adexl/test_states///spectre/ I wanted to add another history file from another view of the same cell, so I just copied at the new history file in the (...)
Hi guys, I was wandering if anyone has ever dealt with history file of ade XL of Virtuoso by Cadence. This files are stored in the folder //adexl/test_states///spectre/ I wanted to add another history file from another view of the same cell, so I just copied at the new history file in the (...)
Hi everyone, I am a newbie in Cadence spectre simulator. I have a 2 ports network and I try to plot the input equivalent capacitance vs. frequency. In ADS I use equation: Cin = imag(Y11)/2/pi/freq. But I don't know how to insert that equation into Cadence. I only used a basic SP analysis. I have read many thread but I cannot find the (...)
You want to either use the Hierarchy editor and assert the proper / intended stop-view (probably "spectre") or look at the views list that ade has (one of the simulator options pulldowns, I forget which). You'll see lists that go like "schematic cmos.sch symbol spectre". Look at what views actually exist under your basic/gnd symbol and (...)
ade->Simulation->Convergence Aids->Initial Condition
Hi I am using Analog Design Environment (ade) IC5141 and HSPICE as the simulator. In stead of using default spectre simulator, I am using Synopsys's HSPICE simulator (I have integrated HSPICE with Cadence's Analog Design Environment , separately), because of certain requirements. The vendor has provided only hspic
hi Dominik, I tried your suggestion as below but I still can't run ade XL. Could you eleborate the detail - command, and exact directory name. I'm using RHEL6.5. Maybe suggest other solution? 1. I created a folder /usr/X11R6/lib/X11 2. create a symbol link. ln -s /usr/share/X11/fonts 3. verified the link by ls lrwxr
Hi, I am trying to take FFT of a time domain signal, at differential LNA output, from 100nsec to 200nsec using spectre ade calculator. However, when i try to evaluate the fft, following error appears. Can anybody suggest what can be the reason for it. Warning - Evaluation error(ERROR : ("putprop" 1 t nil ("*Error* putprop: fi
Hi, all, I am simulating in Cadence ade with spectre. I use a VPWLF source to get a pwl external file as a stimula. In my spectre bench, I have set some variables(Fosc, vdd, for example). I compose the pwl file with these variables in math operations to define the pwl waveform. But when spectre is parsing, (...)
Good Morning at all, I've a problem with the ade L in cadence 6. I've needed to convert a variable in Design Variable from float to integer. But during the simulation, spectre returns an error. I've used a a function round(N), where N is my float number. spectre returns me Function 'round ' is undefined. I hope there (...)
I am simulating a simple one stage differential amplifier with spectre, and trying to see the effect on the offset due to the mismatch of just some transistors. I am able to perform mismatch simulation for all the instances I am able to perform mismatch simulation excluding some instances (i get reasonable results) I am NOT able to just consi
Hi guys. I heard about spectre APS and search information about that. About APS, the video is uploaded to youtube. At the video, the followed option is shown. 101780 However, in my machine, it has just ... 101781 and at ade, simulation option menu -> options -> analog -> [B
Hi everybody, I have a fresh installation of IC 6.16 and MMSIM 12.1 on a linux centos 6.5 64b platform. I'm following a tsmc tutorial just to check that the installation is OK. I'm having some problem with spectre I believe. When I run a simulation from ade L, I get an ade-3036 error in virtuoso CIW, telling me that no log file was (...)
Is this bjt a part of a design kit from a foundry vendor ? If yes, check the proper installation of the kit : you should have the path to the model of this bjt in ade->setup->model libraries and add the path to the model file. If you use a bjt from analoglib, you should put the model name in the "model name" field, and, again, setup the path in ade
Hi all I need to simulate some OP-AMPs and MOSFETs in Cadence ade, as parts of a bigger design. the op-amp (e.g. THS3091) is easily done by importing the Texas Instruments Spice model into ade and simulating it. But, the MOSFETs (e.g. CDS25834F4, that has ENCRYPTED spice model) is faced by spectre with some errors due to (...)
Sure.. Assign a variable for the parameter which you're interested in then do your simulation by sweeping this variable. For instance, Rload=1K (Initial value) then make it as sweeping variable in ade.
Hi, I have a testbench-schematic for an If I start Cadence and open this schematic and ade GXL with the related adexl view and I run the simulation everything is alright. But if I subsequently "Check a
Hi, I am using the ic6.15 version of cadence in CentOS 32bit. When i simulate a circuit using Analog Design Environnement GXL with spectre, the simulation completes and waveviewer opens but nothing is displayed. I can browse in the result browser and select one of the nets and it displays the result. But it does not automatically shows the nets
Have you tried simply editing the model cards to add +delvt0=0.0 mulu0=1.0 in the device params body, and see what happens? If it doesn't barf, then try (say) setting +delvt0=mydelvt0n mulu0=mymulu0n instead, add those variables to the ade list and see what comes of varying them. SPICE type simulators have always let you omit unused params,
The easiest approach is simply to put a series voltage source between the FET gate and its driving source, with (say) v=dVTN to make the (effective) VT variable from within ade. Otherwise you need to drill down into the models/spectre dir and edit the pertinent FET model card, making its VT0 (or whatever your particular model uses) a (...)
I am using Cadence 5.1.41 with NCSU CDK 1.5.1, and I am new to Cadence. I have created a simple schematic in Virtuoso. When I try to simulate the schematic using Analog Design Environment (ade) and spectre simulator, I got the following error. *Error* Errors encountered during simulation. The simulator run log has not (...)
I need a pulse voltage source that slowly gets narrower as the simulation progresses. How do I create a dependent pulse source that used a ramping voltage, or some other input, to adjust the width each time the pulse is high? I'd like the period to remain fixed. Alternately, if I could tell it to go from some width to another width over so many
Dear all, does anybody know how to run a multithred (using all cores of the server) simulation? I use the option: option( 'multithread "on" ) but I notice that the simulation uses lower resources from the server than when I run the multithread simulation using spectre from the ade. Is there any way to use all the cores of the server PC in ocean?
In the ade you'd use calculator to find your output transition timepoint (using cross() function) and the input transition preceding it, and subtract. That calculator expression will also work in Ocean. I do not use bare spectre.
In the ade, click on SETUP then, Simulator/Directory/... Finaly select set your simulator to HspiceD.
Hi all, I have a problem with the simulation of a simple buffer. When I start the simulation from ade-L, I get this error from spectre : Simulating `input.scs' on at 2:58:08 PM, Mon Jun 11, 2012 (process id: 18499). Command line: /usr/cadence/MMSIM101/tools.lnx86/spectre/bin/32bit/spectre \ (...)
Include into what? ... Then I go to Virtuoso Analog Environment: Setup -> Model Libraries and add the path of the created file. That's exactly what I meant! ;-) You can include the text file directly. If you use C@dence ade's spectre, and your model file uses SPICE syntax, don't forget t
Hi there, I'm trying to model mismatch in a circuit - but instead of using the foundry mismatch model I want to put in data I've extracted from characterizing a test chip we've done. I'd like to do this by having a bunch of voltage sources with a mean of zero and a sigma of 1V. I can then use VCCS's to add random currents into the nodes I'm c
Hi - I have a PDK in which I have all standard cells (inverters, nands,etc.) defned in one common .spi file. I have standardlib symbols and used them within my analogic schematic for simulation. I defined on the toplevel global vdd!, gnd!, and also used CDF (VDD netSet vdd!, and VSS netSet gnd!) to be sure that the instantiated inverter ha
Hi everyone, I have a cell "resistor" described in vhdl ams. It compiled fine and created 3 cell views : entity, behavioral and symbol I implemented the "resistor" symbol in a new cell schematic "xbar" I am trying to simulate this schematic using spectre in ade L but I have this error during the netlisting : " ERROR (OSSHNL-116): Una
AFAIR hierarchical netlisting is also possible within Virtuoso's ade. Usually, netlisting uses the foll. default rep- & stopList: repList "spectre cmos_sch cmos.sch schematic veriloga ahdl" stopList "spectre veriloga" So if your memory cell has a spectre view, the stopList makes sure to netlist the cell hierarchi
Hi all, I am using cadence 6.1.4 and i can't find the option of parametric analysis from ade window... In ade window, from tools menu, i just found only 4 options...calculator, result browser, job monitor and dcm... so please anybody show me the proper path to perform parametric analysis?