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24 Threads found on Ahb Burst
From what I understood, in ahb burst mode, master will only give starting address and slave has to calculate the remaining address. But in the picture below (from ahb specification) shows change in address at HAddress pin for every clock. Am I wrong ? Please correct me if I
HI, All: I'm confused when reading AMBA ahb specification. The address is HADDR and thought it should be corresponding to double word or 32bit (HWDATA or HRDATA), since the data port is 32bit width. That's means address 0x0 stands reg_addr_0, address 0x1 stands reg_addr_1. But at burst transfer example in
Hi All, What's the difference between ahb and ahb-lite? Where and when each of the buses are recommended for use? Does ahb-lite support burst transactions? If it does not, why? Thank you!
The address and data cycles are overlapped, pipelined. The data cycle is also the address cycle of the next transfer. See the following document: IHI0011A_AMBA_SPEC.pdf, AMBA Specification (Rev 2.0) Chapter 3.4 Basic transfer "This simple example demonstrates how the address and data phases of the transfer occur during diff
Hi, I from my understanding, we can configure the ahb transaction in many modes like burst of 16, 8, 4, 2, single etc. For example if we are configuring the burst of 16 with data width of 32 bits, which means in a single transaction there will be a transfer of 32*16 bits, within 16 clock cycles (here i am neglecting the initialization and (...)
Hi, I am confused with concept of burst transfer type related to AMBA ahb protocol. (1) If I am using 32 bit data bus then can size of my transfer i.e HSIZE exceed 32 bit? (2)What does 8 beat burst mean and what is maximum transfer size of my data in a burst if my bus width is 32 bit? Please explain me with an (...)
Hello there, Advanced High-performance Bus (ahb) ahb is a bus protocol introduced in Advanced Microcontroller Bus Architecture version 2 published by ARM Ltd company. it has the following features: 1.single edge clock protocol 2.split transactions 3.several bus masters 4.burst transfers 5.pipelined operations 6.single-cycle bus master h
how do i find the data rate of the amba ahb , e.g if i have a clk of 200Mhz and use a data bus of 16bits. does it mean data rate = 200Mhz x 16bits .. how does burst play its role that's because i want to calculate FIFO length and i have 1mbps data going out at the other end - - - Updated - - -
In the ahb specification it is written that: "A four-beat wrapping burst of word (4-byte) accesses wraps at 16-byte boundaries. Therefore, if the start address of the transfer is 0x34, then it consists of four transfers to addresses 0x34, 0x38, 0x3C, and 0x30." My question about the above quote is as follows: If 16-byte is the wrap bou
Hello everyone I have a question about AMBA ahb bus. I wanted to know if there are any similarities between the burst and split operations in AMBA ahb. I am aware of the differences but wonder if there are any similarities. Thanks in advance
Hi all... Is anyone know how to calculate the through put of AMBA AXI or ahb buses... Means if i am transferring a 32 bit 16 burst transfer through the AXI bus at 96MHz, then what will be the data through put of the transfer... Thanks in Advance....
Hi all, I am a bit confused about understanding the time out by using on-chip communication protocols like AMBA (ahb, AXI). For example, if we have two tasks of a real time application. The first task transfers a chunk of data which in turn will be realized from HW component using a specific communication as burst transfer, during that burs
hi all, i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is 16. i must provide 2, 32 bit data to the controller before writing it to memory. As well as when reading from a memory location it gives out 2, 32 bit data out. my processor is a master ahb, has a 32 bit address and 32 bit data bus. How can i connect these 2 togethe
Hi Experts, Why the addressing limitation in ahb is 1kb , is there is any speccific reason. Thanks and regards, Kanimozhi.M
BUSY is certainly used by some ahb designs, although many masters do not require it. If you are designing a general purpose slave that can be used in any system, you should make it support BUSY (if it is burst capable). Otherwise, check with the designer of the master to see whether it uses BUSY. A very simple example - consider a CPU which is b
It is up to the master how it responds to an Error during a burst. It is allowed to terminate the burst, or to continue the burst. What it does with the error is also up to the master - it can try the access again, or it may be that it reports a problem (blue screen of death style). ARM processors will typically continue the (...)
why we need the hburst(incr,wrap) input signal for a ahb slave(interrupt controller)?
HI kindly help me out...... In ahb/AXI protocols if the size of transfers is less than the bus width (narrow transfers), for example , if it is 1byte transfer on a 32 bit bus and offset address is 1 , transfer is on second byte lane (ahb). (Little Endian) similarly for 32 bit transfer on a 64 bit bus trasfer starts on 32-63 bits (from 5-
In a burst transfer who is responsible for increasing the address?The master or the slave? Should the slave read the address from the haddr input on every clock cycles,or read the address only when htrans=NONSEQ and increase it according to hsize and hburst? Thanks
Can Slave give a retry response when htrans is sequential? Slave has a write data fifo to store hwdata, if burst type of master is unspecified length, how can slave decide whether write data fifo has enough rooms for following data of write transaction?