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114 Threads found on edaboard.com: Ahb Bus
It's the forst time I'm dealing with bus. If you find AXI4 overwhelming for the first time, start with ahb-Lite spec, then go for AXI4-Lite and finally AXI4 itself. If you are going to write a BFM on your own well then good enough. Getting a free BFM (to understand how they are coded and how they work) can be challenging. Her
Hi. I found coretex M0 MCU module's bus interface has not HbusREQ and HGRANT, and HRESP when i trying to implement with ahb bus. Is there anyway to use ahb not ahb_lite. I can't use multi-layer interconnect system. only I can use ahb.
i am doing a project on AMBA-ahb interface with the referance AMBA specification 2.0.can any body help me to get the source in uvm(slave side).
i am doing a project on AMBA-ahb interface with the referance AMBA specification 2.0.can any body help me to get the source in uvm.
HI. Well, its depend on the bus size. But I want to know normally roughly how many the gate count of AXI, ahb bus?
Have you decided on your Master and Slave modules? The ahb bus would provide data to be transferred between b/w the M and S. Without a Master and Slave an ahb i/f would be meaningless. Download the ahb Lite spec from ARM and read it too. oh, btw - Have you solved the problem of your thread - What am I do if I have to (...)
One proven and tested way to do this is to use a BFM (bus Functional Model). The BFMs generally cannot be synthesized and they are connected in a test-bench. e.g.- AXI BFM, ahb BFM, etc. I will not explain how BFMs work as a google search on the above will yield all infos you are looking for!
I have question on ahb bus ? Question ? 1 (related to issue faced in closing timing.) Basically I am new to ARM & its bus protocol, I have just started to work on it, so have lot of questions. I am referring to this diagram e.g . Can I say that arbiter + muxes + decode selection
Hi All, Why AXI bus is faster than ahb? Thank you!
Hi All, How does the multi-layer ahb bus work? Are there any useful articles you can recommend? Thank you!
It should basically check for the correctness of the ahb protocol..Whether it is in sync with the ahb standard...
Hi. I am willing to connect between ahb bus and sram. So I need the bridge that it can be connected ahb bus and sram. I have got sram.model but i don't know how can connect between sram and ahb bus. Is these any supported bridge?
There's no hsplit in ahb-lite.
FULL invert can be used to drive hready in write. Empty invert can be used to drive hready in read. But it would hold ahb bus for too long when fifo is full or empty. Or you can poll full/empty before do real write and read.
Hi i have a little confusion on the ahb Protocol and i need help. 1) why we use a delayed version of HMASTER on the HWDATA MUX (the multiplexer that used to connect the data bus of master to the slave) 2) i know that we keep the pipelining on ahb Protocol by delay the data(HWDATA) one cycle before the address(HADDR) (as i understand)
what is the major difference between verilog HDL and VHDL???? Which is best in designing the AMBA ahb, ASB,APB,AXI????? The biggest difference is VHDL's a strongly typed language and is significantly more verbose than Verilog. Either language will work well at implementing any if those bus protocols. Both lan
IF you have a multi master ahb bus Matrix and if you wants to go with self-motivated arbitration scheme, then you can go with a Round Robin arbitration scheme. Check the master zero first, if there is a request for any transaction then do the transaction then check for master one, then do the same. if the master is not requested for any transaction
You can, but throughput isn't very good, as APB takes at least two cycles per transaction. Better to use ahb.
Hi All, Could someone provide SHORT and CLEAR guides for ahb, OCP and AXI bus protocols ? Are there GOOD books for these subjects? Thank you!
can anybody explain the speed and data rate of AMBA ahb AMBA APB AMBA AXI ??