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V(in, out) <+ 0.0; //for on state I(in, out) <+ 0.0; //for off state You also can describe smooth switch by tanh(). You can see many examples in "ahdllib" and "bmslib", if you have Cadence dfII.
Hi all, what is the design of SR flip flop for voltage mode boost converter i try this circuit and it doesn't work like ideal one from ahdllib on cadence { } :drevil: :thumbsup:
Hi, i have a problem with the op amp in the ahdllib in Cadence. I connected it as voltage follower with sinusoidal Vin+ (Amplitude 2.5V, f=10k), Vdd=5V. I set the following parameters for the opamp: gain=10000 frequ_unitygain=100M rin=10M vin_offset=0 ibias=0 (input current) slew_rate=10M rout=50 vsoft=4.9 iin_ma
Hi every one i work on a simulation project in CADENCE Schematic, but i lost it's ahdllib library. i need it asap for simulating digital circuits. thanks all.
Hi, ahdllib -> rand_bit_stream or you can build your own random data source in Verilog-A
Hi, Has anybody used ideal opamp from cadence ahdllib. I am trying to simulate it with Vsupply_p=1.2V, Vsupply_n=0V and Vref=600mV in unity gain configuration. However, for a sine wave input, output is just a constant dc voltage. I tried to change different parameter values but it did not work.
Couple suggestions: 1. Check Environment (Setup/Environment/Switch View List). Must contain "veriloga" 2. Use resistor models from built in libraries: ahdllib (veriloga model); and analogLib (spice model). See if you are able to probe currents/voltages/dc operating points. If the result is still negative: check your library version with spectr
Hi everyone, I am using verilog-A to build up a behavior model of opamp for LDO. My opamp is a differntail input folded cascode and single output amp, and I am going to limit the output range of it between vdd-2Vov and 2Vov. I looked at the opamp example in the ahdllib, which is in the virtuoso library, and can't figure out the code in "soft output
OK, in "functional" lib there is "multiplier", and in "ahdllib" there are actually am_ and fm_ modulator and demodulator (and pcm_). At least this is what I have. These libs are Cadence-supplied.
I think there is something wrong in the circuits? the opamp is from cadence ahdllib,both of the gain and GBW are set to 69dB and 400M.the ac result is ok,but this fully differential opamp cant work in my loop? is anything wrong ?
Hi, I am a fresh in the ADC design. now i wanna test a 4b flash 52Mhz quantizer with this ahdl code in virtuso, plz give me some description of that, appreciate a lot.
I'm looking for a sample veriloga code to model a fully differential opamp. Imran. You could start from examples from the Cadence ahdllib/opamp s. $CDS_INST_DIR/tools/dfII/samples/artist/spectreHDL/Verilog-A/analog/opamp.va ... and change the non-differential output to a differential one, perhaps using the ahdllib/di
For this purpose, you can use the simple amplifier in the ahdllib library (or base your own design on that).
If you have the analogLib: pvcvs2 or ahdllib multiplier or functional multiplier.
use rand_bit_stream from ahdllib
in the analogLib, No existing ideal comparator, you can find it in ahdllib. and you need add "veriloga" view in the switch view list to the environment.
Hello, when i use a ahdllib's componet in a schemtic i get an error, why?? How can we know if you don't tell us, when you get it, and what is its message? can't i use this library? Sure you can! When i go on the properties of ahdllib's componet, when close the window
Hello . I am trying to get the DNL from 10 bit sar adc ? I am using , cadence library "ahdllib , dac_10bit_ideal " to convert the 10 bit ADC ramping output " D9:D0 to analog signal . Then using , " cadence library " ahdllib , dac_dnl_10bit " to get the DNL of the ADC ? It supposed to output a histogram file or someting . But I dont see any file ?
Hi everybody.... Where can I find information about the component of the Cadence libraries ahdllib and analogLib. Thanks
Hello all, I have just designed a 8 bit ADC. I was wondering how can find out the INL/DNL of my ADC? I know that I could use the ideal 8 bit DAC that is in the ahdllib in Cadence. But I just don't know how to set the attributes in the ideal 8 bit DAC. Can anyone please tell me how to do that? Does that ideal 8 bit DAC work with hspiceD? I would