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56 Threads found on edaboard.com: Amba Ahb Bus
i am doing a project on amba-ahb interface with the referance amba specification 2.0.can any body help me to get the source in uvm(slave side).
i am doing a project on amba-ahb interface with the referance amba specification 2.0.can any body help me to get the source in uvm.
Hi. As I know, We can make the bus matrix by using like NIC501 or something like tools. My question is that how can we verify the bus matrix? and what kinds of methodologies are existed to verify the bus what I made? Practically, I want to know that how to do this in Practically. Does any help this?
what is the major difference between verilog HDL and VHDL???? Which is best in designing the amba ahb, ASB,APB,AXI????? The biggest difference is VHDL's a strongly typed language and is significantly more verbose than Verilog. Either language will work well at implementing any if those bus protocols. Both lan
Hi, Most of the Design (SoC), the APB bus is used for register configuration. For bulk data transfer (eg: Video, EMAC) in amba we are using ahb or AXI. AXI is better than ahb.
There is a complete amba bus specification here: . Enjoy your design work!
I have read that amba ahb bus bandwidth (in bps) is 16 times clock frequency. Is it true? I read this in one of the ppt presentation downloaded from net. I want someone to confirm this. If this is true then if clock frequency is 25MHz then can I assume bus bandwidth to be 400Mbps for my amba (...)
Hi, I am confused with concept of burst transfer type related to amba ahb protocol. (1) If I am using 32 bit data bus then can size of my transfer i.e HSIZE exceed 32 bit? (2)What does 8 beat burst mean and what is maximum transfer size of my data in a burst if my bus width is 32 bit? Please explain me with an (...)
Hi, (1) How to determine number of bus cycle for read operation/write operation for amba ahb protocol. If I say bus cycle required for read /write is 4T states, then is it appropriate to say that for any amount of transfer on the bus the number of T states required is 4? (2) Does clock frequency is (...)
Hi, I am implementing arbiter module for amba ahb protocol for real time masters in verilog HDL. I want to know what value should I specify for HCLK signal. And what value should I consider for as my bus speed/bus bandwidth/bus rate? At least suggest me the source from where I can get this information. (...)
Hi; I am implementing arbiter module for amba ahb protocol in verilog HDL. For that I am considering real time masters having constraints in terms of deadline and service cycle. Now I am stuck at a point and want to know how the master convey this constraints to arbiter so that the arbiter will do the scheduling and grant the bus to one (...)
how do i find the data rate of the amba ahb , e.g if i have a clk of 200Mhz and use a data bus of 16bits. does it mean data rate = 200Mhz x 16bits .. how does burst play its role that's because i want to calculate FIFO length and i have 1mbps data going out at the other end - - - Updated - - -
hi guys, i have to do some calculations of how to handle the ahb bus bridge (connecting 1Ghz ARM and WLAN) , e.g i have to make a formula ( or excel sheet) for the wlan speed to bridge clock speed , e,g if i connect a 11Mbps wlan through a bridge to this ahb bus operated at 1Ghz( although it would also spare time for other (...)
i am doing a project on amba-ahb interface with the referance amba specification 2.0 from ARM. can any body help me to get the source in vhdl.
Hello everyone I have a question about amba ahb bus. I wanted to know if there are any similarities between the burst and split operations in amba ahb. I am aware of the differences but wonder if there are any similarities. Thanks in advance
Hi anbuonlymevlsi, As nisshith said, for a 4 bit ALU there is no need of any pipeline mechanism. Here is an example where we can insert a pipeline mechanisms. Have you heard about the ARM's amba ahb protocol, in that protocol there is a pipeline mechanism. There is a shared Address bus for read and write operation. So if we are performing a (...)
Hi all... Is anyone know how to calculate the through put of amba AXI or ahb buses... Means if i am transferring a 32 bit 16 Burst transfer through the AXI bus at 96MHz, then what will be the data through put of the transfer... Thanks in Advance....
Hi I have a question about opencores pci to wishbone bridge. In the test bench, the designers have set the pci clock period to 30ns (33 MHz) and similarly set the clock period of wishbone clock to 10ns (100 MHz) to test it. From this it makes sense because pci bus has a frequency of 33 MHz and wishbone bus has a frequency of 100 MHz. But i
Hi, Here's a tutorial presentation I had created for ahb bus training at my office. I've kinda put in only the relevant info need so that by the time you're through with it you will know at least most of the ahb bus details. Hope its useful! Thx
Hello, I have a question about a master to slave transfer on an ahb-lite bus. Suppose, an ahb-lite master initiates a transfer to an ahb-lite slave. If the slave can respond at once, everything goes fine. But if it takes the slave many cycles to do the job the slave must issue an HREADY='0' for as long as it's (...)