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i want to make a design for amba 3 ahb-Lite Protocol i have the design for master and slave but i have a problem when i make the test bench the value of the HRDATA is do not care ,on the other hand the slave design return the correct value for HRDATA but the master does not, is there a special method to connect the master and slave together ???
i am doing a project on amba-ahb interface with the referance amba specification 2.0.can any body help me to get the source in uvm(slave side).
i am doing a project on amba-ahb interface with the referance amba specification 2.0.can any body help me to get the source in uvm.
Hi, I am asking about ahb single transfers. Is it possible to have Back-to-Back single transfers ? There will be and arbitration phase before each transfer which will not allow back-to-back singles, Is that right ? By back-to-back transfers, i mean two adjacent address phases for the same master I am referring to amba specifica
Hi. As I know, We can make the bus matrix by using like NIC501 or something like tools. My question is that how can we verify the bus matrix? and what kinds of methodologies are existed to verify the bus what I made? Practically, I want to know that how to do this in Practically. Does any help this?
HI, All: I'm confused when reading amba ahb specification. The address is HADDR and thought it should be corresponding to double word or 32bit (HWDATA or HRDATA), since the data port is 32bit width. That's means address 0x0 stands reg_addr_0, address 0x1 stands reg_addr_1. But at burst transfer example in
The ahb is part of ARM's amba standard - you can find it here: All you have to do is write a wrapper for your FIFO...
The address and data cycles are overlapped, pipelined. The data cycle is also the address cycle of the next transfer. See the following document: IHI0011A_amba_SPEC.pdf, amba Specification (Rev 2.0) Chapter 3.4 Basic transfer "This simple example demonstrates how the address and data phases of the transfer occur during diff
Hi All, I'm seeking for amba ahb Specifications, but found ahb-Lite only. So, where can I download the ahb-Full Specifications? Any links, shares? Thank you!
what is the major difference between verilog HDL and VHDL???? Which is best in designing the amba ahb, ASB,APB,AXI????? The biggest difference is VHDL's a strongly typed language and is significantly more verbose than Verilog. Either language will work well at implementing any if those bus protocols. Both lan
Hi, Is there an opensource PLB to amba ahb Bridge? can you give me any link for this. it would be much appreciated. regards,
Hi, Most of the Design (SoC), the APB bus is used for register configuration. For bulk data transfer (eg: Video, EMAC) in amba we are using ahb or AXI. AXI is better than ahb.
Hi, These are the amba specification from ARM ACE, ACE-Lite, AXI4, AXI4-Lite, AXI4-Stream, AXI3, AXI3-Lite, ATB, ahb, ahb-Lite and APB protocols. You can refer ARM's this link for more details. Click the amba in the above link.
can anybody explain the speed and data rate of amba ahb amba APB amba AXI ??
I have read that amba ahb bus bandwidth (in bps) is 16 times clock frequency. Is it true? I read this in one of the ppt presentation downloaded from net. I want someone to confirm this. If this is true then if clock frequency is 25MHz then can I assume bus bandwidth to be 400Mbps for my amba ahb bus Waiting for (...)
Hi, I am confused with concept of burst transfer type related to amba ahb protocol. (1) If I am using 32 bit data bus then can size of my transfer i.e HSIZE exceed 32 bit? (2)What does 8 beat burst mean and what is maximum transfer size of my data in a burst if my bus width is 32 bit? Please explain me with an example!!!!!:roll
Hi, (1) How to determine number of bus cycle for read operation/write operation for amba ahb protocol. If I say bus cycle required for read /write is 4T states, then is it appropriate to say that for any amount of transfer on the bus the number of T states required is 4? (2) Does clock frequency is related to bus frequency and how can we d
Hi, I am implementing arbiter module for amba ahb protocol for real time masters in verilog HDL. I want to know what value should I specify for HCLK signal. And what value should I consider for as my bus speed/bus bandwidth/bus rate? At least suggest me the source from where I can get this information. Waiting for your urgent reply!!!!!!:roll:
Hi, I am implementing arbiter module for amba ahb protocol for real time masters in verilog HDL. For that I need to calculate deadline for the real time masters. It will be calculated as: Deadline = Execution time + Arrival time of request + slack(assumed). Hence I need to know the amount of data the master is going to read or write for calc
Hi; I am implementing arbiter module for amba ahb protocol in verilog HDL. For that I am considering real time masters having constraints in terms of deadline and service cycle. Now I am stuck at a point and want to know how the master convey this constraints to arbiter so that the arbiter will do the scheduling and grant the bus to one of the
95863 i read the protocol 3 times and I think i understand it. Based on the protocol, the address decoder is combinational logic. its inputs are just the address from the master, so its outputs are in the same cycle with the address cycle. But ahb's data cycle is one cycle after the addr cycle. So in the figure, at some
Hi ALL, I have a question about when the ahb can be deadlocked. I get this question in the amba protocol pdf from ARM but it seems that it's not clear enough for me. And I found something in the ARM information Center, which says: " Does a master need to issue non-LOCKed accesses when accessing a sequence of ahb slaves ? Applies to: (...)
how do i find the data rate of the amba ahb , e.g if i have a clk of 200Mhz and use a data bus of 16bits. does it mean data rate = 200Mhz x 16bits .. how does burst play its role that's because i want to calculate FIFO length and i have 1mbps data going out at the other end - - - Updated - - -
hi guys, i have to do some calculations of how to handle the ahb bus bridge (connecting 1Ghz ARM and WLAN) , e.g i have to make a formula ( or excel sheet) for the wlan speed to bridge clock speed , e,g if i connect a 11Mbps wlan through a bridge to this ahb bus operated at 1Ghz( although it would also spare time for other peripherals from the tim
on what condition slave will give RETRY/SPLIT response to master in amba ahb ?
Yes interconnect checks same. I think the checking equation is added in amba 4 spec.
i am doing a project on amba-ahb interface with the referance amba specification 2.0 from ARM. can any body help me to get the source in vhdl.
does a single master system need locked access?
Hi, I have a doubt regarding HTRANS in ahb. In a HTRANS states are idle, busy, nonseq, seq. During transaction is BUSY state occur after IDLE state.can any one explain.
hi i am doing amba ahb Lite as PG Diploma project and want help in verificaton of slave. can anyone provide me data relating how can we use verilog for its verification. please reply. thanks
hi i have done with random control and address generation for my amba ahb project also i have applied it to master and have taken two separate output file(1 giving input to slave 2. taking output from slave) problem is that i have to compare both file manually. A i m thinking for comparator logic which will automatic check for error. please gui
Hello everyone I have a question about amba ahb bus. I wanted to know if there are any similarities between the burst and split operations in amba ahb. I am aware of the differences but wonder if there are any similarities. Thanks in advance
Hello to all...... If master asserts htrans as busy and in the same cycle slave gives hresp retry and hready low for the previous transfer as response then what should be the htrans in the secons cycle of retry.
Hi All, I have have a doubt reg the timing parameters available in the protocols like amba ahb, AXI etc. My question is: what is the use of the timing parameters provided in the spec? 2. As a designer how we should interpret it and while coding the protocol using Verilog HDl, what is the exact place where we should use it? pl explain me the conc
Hi anbuonlymevlsi, As nisshith said, for a 4 bit ALU there is no need of any pipeline mechanism. Here is an example where we can insert a pipeline mechanisms. Have you heard about the ARM's amba ahb protocol, in that protocol there is a pipeline mechanism. There is a shared Address bus for read and write operation. So if we are performing a burst
Hi all... Is anyone know how to calculate the through put of amba AXI or ahb buses... Means if i am transferring a 32 bit 16 Burst transfer through the AXI bus at 96MHz, then what will be the data through put of the transfer... Thanks in Advance....
Hello all... I want amba- ahb assertions can any one help me...?
Hi all, I am a bit confused about understanding the time out by using on-chip communication protocols like amba (ahb, AXI). For example, if we have two tasks of a real time application. The first task transfers a chunk of data which in turn will be realized from HW component using a specific communication as burst transfer, during that burs
Hi I have a question about opencores pci to wishbone bridge. In the test bench, the designers have set the pci clock period to 30ns (33 MHz) and similarly set the clock period of wishbone clock to 10ns (100 MHz) to test it. From this it makes sense because pci bus has a frequency of 33 MHz and wishbone bus has a frequency of 100 MHz. But i
Hi, Here's a tutorial presentation I had created for ahb Bus training at my office. I've kinda put in only the relevant info need so that by the time you're through with it you will know at least most of the ahb Bus details. Hope its useful! Thx
Hello, I have a question about the HREADYOUT signal of an amba ahb slave: Is it allowable for the slave to drive the HREADYOUT signal low (HREADY <= '0') when it's not being addressed by any master? Or must it assert an HREADYOUT <= '1' when it's not being addressed. This is strictly a protocol compliance question - this would dictate the
hi all, Im involved in amba ahb RAM memory controller design(Internal RAM used by ARM following FSM design approach.....which FSM moore or mealy will be more suitable for these purpose? and why?And regarding the number of states of the fsm? please provide me any links/references
Hello, I have a question about a master to slave transfer on an ahb-lite bus. Suppose, an ahb-lite master initiates a transfer to an ahb-lite slave. If the slave can respond at once, everything goes fine. But if it takes the slave many cycles to do the job the slave must issue an HREADY='0' for as long as it's busy - This action would
Hello people, I'm in the process of learning about ARM's ahb amba bus. My goal is to integrate existing VHDL designs on a single SOC's. I've read the amba 2.0 specs and there're quite a few things that aren't clear to me. First question: How many addresses does a single ahb slave have? The address width is 32 (...)
Hello everybody, i am new in Hardware design have a project in designing an AXI Bus in VHDL and testbench in SystemC (Co-verification). I read some documentation and have understood how it works, now could some experienced persons tell me which are the steps i should follow, for example what are the different VHDL entities i will need (Channels,
I hope you get it in amba bus specification easily
Hi I have a naive question about amba bus protocols If there is ahb bus on one side (say left hand side) and there is APB bus on the other side, then you need a bridge. The question is do you need ahb2Apb bridge or Apb2ahb bridge or both In which case, i need only one bridge and in which case i need both bridges? (...)
Hi friends, I have been working very very hard for the past few days on the arbiter part of the amba ahb bus architecture. I am using a fixed priority algorithm for allocating grant to the bus master. I tried simulating the arbiter verilog code on modelsim with the testbench that I wrote. I was very disappointed. :cry: Even a simple grant signal
Hello friends, I am a beginner, working on modeling the amba ahb. I've gone through the ARM documents and certain things regarding SPLIT and RETRY are not clear to me. These are very basic questions, but pl help me for I need to clear my concept. My questions are: 1) Can a split capable slave cause a "split" in the middle of a burst operati
Hi all, I have some difficulty by understanding the reason why only one master can own the bus system at the time even if another master do not want to access the same target which responds the first master request. which penalty shall the bus to face if it is suitable to deal with this option? Thanks Mido