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23 Threads found on Analizer
Hello, I want to do a three-phase energy network analizer, which can evaluate in real time the power factor and THD. for that I must do the DFFT (discrete fast fourrier) in real time. What DSP board (development kit) do you recommend me? I need a development board kit to start. I need something cheep too.
Hi. I have find this document wich suggest the use of a passive probe in 1:10 to attenuate the signal to a spectrum analyser in order to be able to use signals above +20dBm. The theory is easy, the 9M resistance is a voltage divi
My MS2601 has a fault. Maybe something is not locking, or there is ripple on a supply line. The display is most unsteady and looks like 'hum' modulation of any spectrum I'm looking at. Anyone familiar with fault finding in these analizers? I have the books.
hi if you had a protocol analizer, you can check it.with a good CRO(may be a storage one), you can check can even use some hardware simulators to check it. or make a hardware and try read and write ml
To convert jitter-phase noise see: Clock (CLK) Jitter and Phase Noise Conversion - Maxim to measure VCO phase noise, you can use a spectrum analizer, if you don't have a dedicated instrument. This will limit the lower offset you can measure, to few kHz (due to freq instability). Another (che
hi. i'm working with rfm12b by AVR and Bascom. i have a problem with it. after 3 month i just can initial it and i can see the spectrum of the radio frequency that it make on spectrum analizer. but i can not send any data. i mean because it use fsk Modulation if it send any data i had to see a moving of the spectrum but i didn't see anything.
First possibility is to use a dedicated instrument such as Agileng signal source analizer. It has a specific test mode to measure freq vs time. Another good option is to use a spectrum analizer with FM demod option. Setting the spectrum freq at final PLL value, just trigger properly at the correct event, you'll see when the signal enter the rece
Biff VNA has not the required accuracy for this kind of measurements. Inductor's companies use impedance analizer (Agilent/HP 42876A) to do the job. If you need such a high Q, why don't you buy inductor already characterized (such as Coilcraft 132 series, in the range you are interested they are guaranteed up to 3A rms nad Q>200)? Mazz
what is protocol analizer software?
I don't think so. VNA is used to small signal response of circuits. It uses a sweeped CW signal and detectors to evaluate S parameters. Noise figure is measured with a good accuracy with a noise source and Y-factor method, so you will need a receiver (typically a spectrum analizer or a dedicated instrument) to do it. I hope it can help. Mazz
Hello I want to measure S parameters of bipolar transistor. Have I to provide matching for them when I connecting it for analizer equipment?
i would like to design spectrum analizer using fpga and vga monitor . just consider vhdl+code+vga monitor +3-4 switches and such devices operates upto 50-80mhz i need all expert help here to complete this nice project
To bias the transistor use bias-tee. Are lab accessories (essentially is an LC network) that permit to add a DC to a signal. Connect them to your network analizer and calibrate it. I hope it can help. Mazz
anybody has an experience with circuit breaker analizer?
Hi, thank u for your attention. I am doing FPGA verification with ISE. The codes are fixed. signals in CDC file will be modified. Sometimes when the signals in CDC are too many, then after PAR, there will be timing violations. By using timing analizer and FPGA editor, I can find the crital path and located it in the PAR's netlist. But that's
No, it is misunderstood i don't want to make my CPU, i want to make my logic analizer with FPGA and some uC. I need URL to sam logic analizer project. P.S. Thanks on fast reply.
Not an easy task. Usually a problem found to measure I & Q. One way is to have calibrated paths to a combiner, with a certain known and trimmable phase and amplitude difference between two paths: when the output is ZERO (a good sensitivity is achieved with spectrum analizer), the two signals are opposite at combiner input. You can deembed single
I think there are two main reason for deembedding in EM simulators: 1)Eliminate the discontinuity at the port when a port is close to the bondary. 2)to behave like a network analizer.. bye Added after 2 minutes: I think there are two main reason for deembedding in EM simulators: 1)Eliminate the discon
Hi sriramsv, Normally we use both FPGA and simulation to do Pre-Silicon Validation. For FPGA the tools are Logic analizer, FPGA board. For Simulation the tools are Simulators from any EDA Vendor.
I have one of these, recently obtained because it seems to have gone faulty. It fails all memory diagnostics, the file system seems full & I cannot empty it & there are spurious chacters appearing on the screen. I think that the NVram may be faulty. has anyone any experience of the insides of these Spec/analizers?