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31 Threads found on edaboard.com: Analog Design Issues
Can anyone pls explain to me in digital layout what are the factors that affect 1) Timing (causing timing violations) 2) power 3) area (if i have missed on any other factor that is considered while doing digital layout design kindly include that too pls) For a analog layout with scaling technologies so many issues are considered (...)
Basically, tight enough to do a decent crystal oscillator justice. Also the ad1955 is a decent chip IRC. I'm entertaining the notion to have a section sporting two clocks and a multiplexer for the whole deal. I was thinking the oscillator would run the best if it's on its own little island. Only the connection would be weak
Hi all! I design mixer for the first time with HBTs. Some quick questions: 1. How should the switching quad be biased regarding the Vce voltage? (the analog for CMOS is minimal VDS to get almost ideal switch...) 2. How should the transcoductor and switching quad be biased? Thanks!:)
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Hello, I am simulating inductive coupling in cadence 6, virtuoso analog design environment. I am trying to study the bevaiour of the circuit with change in the coupling coefficient/mutual inductance between the pair of coils. I am running sp analysis to look at S parameters. I observe that if I set a single value of k (coefficient of coupling) v
please suggest link or paper for explanation Any analog Circuit design textbook shows this interrelation.
Hello everyone, In my test bench, I have two instances of a top level design, which has two separate blocks (one is RTL (representing analog), one is completely digital (routed with Encounter, and SDF obtained from Primetime STA)). I am not sure how to specify the SCOPE for ncelab. I can specify one instance: SCOPE: test_bench.top_
I'm looking for a few book recommendations. I've graduated with an EE degree, and now hold a hardware design position at a small company, but I feel like I'd like to learn a lot more. Obviously, having completed a 5 year EE program, I've got a reasonable grasp of the the basics, but the more I learn about the practical stuff at work (Signal Integri
Hi All, I am an analog layout designer (Beginner) and want to built my career in the field of analog design. It will be helpful if anyone tell me how to start and what should be the step-by-step procedure to make myself comfortable with the design issues. Thanks in Advance Sorabh
is it related to digital layout or analog layout ? there are number of issues you might have to consider. only designer could give you the design to do layout of design. all relevant information must required. Foundry related Process information. please lets discuss about your question more (...)
I would appreciate if any body give me some help about this issue You can find a good summary on layout symmetry issues in Behzad Razavi's book "design of analog CMOS Integrated Circuits", Chap. 18, Sec. 18.2.2 Symmetry . In your JPG, the layout geometry (d) is better than (e) because of better D1-D2 symmetry. Take care t
Hi, I am working in my thesis about design of a esd circuit protection (for analog circuit) and I have many information about this. However I need information about simulations issues in hspice. Any one can help me? :?: :?: :?:
I am going to begin first ever IO layout... Is there is any special point I should take care..?? Is it different that core analog layout.. any relevant document will be of great help...
dear hock I hope the thread is still active. I have the same issue (Hit Kit 3.70 installet on red hat). When I run analog Environment the models are not automatically loaded. Could you help me please?
Current DRC checkers are not focused on checking circuits for issues that are specific to ESD. I would like to here from others to see what is being done at your company concerning checking designs for ESD robustness. I've placed this in the analog IC design and Layout section because ESD is much harder in an (...)
Hey I highly recomm Johns and Martin's analog book, which contains two chapters discussing opamp design. I'm sure you can find the solution manual here.
not sure whether my opinion is true... in 45nm, the mask is so expensive... every design flaws will make the company lose a lot of money and lack a lot behind to competitors... so I don't think a big company allows freelancer to design the analog part (which is the most critical one), it also involve ownership issues (...)
QQ group number for analog design issues discussion : 17359730 this group is for analog designers' communication more conveniently join in us ,right now :)
Hi, guys The attachment is from Allen and Holberg's book--<analog Circuit design>> for the CMRR simulation, my question is: from the model (b), how can I get the formula 6.6-3:Vout/Vcm= ?Ac/(1+Av-(?Ac/2))? According to Allen's errate, there are two issues for this model: Fig. 6.6-7(b): The polarity of the upper Vcm source should (...)
What kind of design u re talking about?. Is is analog or digital. Is the inference of the inductance intentional or unintentional. If it is undesired as an example in interconnects then it leads to LCR effect between to closely spaced buses. In general the effect is CR but for 0.13um and down the effect is LCR. This leads to cross talk between two