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59 Threads found on edaboard.com: Analog Rules
Hi, This is my first post and hope you can guide me ;) I own this old one osciloscope and want to make back to life, if this worth. I powered and no image get, i move and get sometimes a image line and sometime is i move i get some image. Can be some cold solder? When the stuff start works fine like 1 min and goes black and need to tap and image
Separating GND kinds (power, analog, digital) is always welcome for signal integrity purpose, but how strict and how efficient necessary, it depend on design requirements, component specifications and dynamic aspects such as energy level involved and bandwidth of signals.
Hi, I know about mixed signal design flow using either cadence or synopsys tools. But I am not clear with the technology used to design the analog parts. Let say, I design my digital blocks using 130nm, then how can I ensure that the analog parts will be according to 130nm technology? Does the foundary has certain rules for the (...)
Hi all, I have been doing analog layouts since three years and now I have been projected to the memory layout and the details are not known, project is for 6 months. Somebody please let me know whether this is a good move or I should stick to analog layouts? If you know, also please let me know how having experience in memory layouts can add
Hi all, I have one doubt in Layout mos structure.What is the reason behind that the poly gate extension from the diffusion layer both top and bottom.if anybody know that please reply me.....
Forum rules say "Don?t reply to posts when you can?t help with the asked question" At least in the analog IC design forum, TMSC (an IC fab) and 0.35 (0.35 ?m technology) can be considered known technical terms.
Hello! Did anybody see or know where I can find figure "number of produced analog chips per minimum feature size"? Thanks advance
Hello, Please help me with the following questions : If EM fails at the metal to diffusion contact, let's say source/drain contact and we cannot play with the w/l or no of contacts , is there a way to fix EM there ? In ESD protection scheme , we put diodes at inputs to clamp the voltage. Considering that, why can't antenna diode save from ES
I am using the automatic routing tool under 'Route' in Layout XL (IC6.1.6) and cannot figure out where the rules for spacing are located. I'm laying out a simple OpAmp with a current mirror and implementing the common centroid technique for a few of my mosfets. When running the routing tool everything routes correctly except the contacts. The cont
Hello friends, I have few questions related to cmos layout/fabrication process that I'm unable to find answers to , please help : 1. Why do we have STI ? specially in lower technology nodes compared to larger nodes ? 2. Why do we need to meet minimum density rules ? What's the issue if density is low at some areas causing a groove during cm
Questions : 1. Why do we have STI ? specially in lower technology nodes compared to larger nodes ? 2. Why do we need to meet minimum density rules ? What's the issue if density is low at some areas causing a groove during cmp ? Why is the planarity needed ? 3. What is requirement to put dummy's at top and bottom more stringent at lower techno
I have a transient simulation running in Cadence. I am powering 'down' my analog circuit in the middle of this simulation. How do I check for floating nodes after the circuit has been powered down ?? On the schematic I have already done Options -> Check rules setup -> Floating nets = Warning I will appreciate the reply.
Why don't you refer to known working IR remote control protocols like RC5? Why not generating the 38k in software respectively by a PWM output? You definitely don't need analog components besides IR-diode, current limiting resistor and IR receiver.
hai friends, Am just trying to route an analog board,in that can a track pass between 2 pins of a transformer?91809 this type of routing is wright or wrong ?
Dear all, I am working on an analog IC design project using TSMC 130nm technology. I have all the schematic, layout, simulation models but missing LVS, DRC rules for layout verification (assuraDRC.rul, extract.rul, compare.rul). Does anyone have these files? Can you please share with me if possible? I need these quite urgent and contacted MOSIS
I see many experienced analog designers that impedance match the non-inverting and the inverting pins when an op-amp is internally compensated. Do most of you guys do this too? If not, what are rules of Thumb for handling op-amps that compensate bias currents internally?
I'm a analog research assistant that often has to make my own custom digital cells. I was hoping to get a few quick comments or rules of thumb you may follow regarding digital device sizing. If digital power is not a critical concern for me, is there any reason to prefer or avoid a minimum-W nmos device in my inverter? Currently, I'm under the
does any one have this Phd thesis: "Baseband Continous-Time Sigma-Delta analog-to-Digital Conversion for ADSL Applications" Shouli Yan thanx
Following the thread, I have done some advances. Now here is an odd problem I am facing with Cadence IC5141. I have done a layout of the simple voltage divider circuit using the RNNPO_RF model file in UMC018 library. images.elekt
Hi values of W and L depends on your design and what you want to design,for example if you want to design a logic gate you must consider rise time and fall time of gate and also load capacitance and from formulas choose a initial value and then simulate and change this value to reach to the best value, about L we usually choose it as small as pos