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63 Threads found on edaboard.com: And Circuit Design Vhdl
D. Perry. vhdl (3rd Edition, Mc. Graw-Hill, ISBN 0-07-049436-3). Z. Navabi. vhdl (2nd Edition, Mc. Graw-Hill, ISBN 0-07-046479-0). V.A. Pedroni. circuit design with vhdl (MIT Press, ISBN 0-262-16224-5). i need soft copies of thes books
hi every body I'm new in FPGA. but I've worked on Altium pcb and schematic a lot. but not the FPGA design yet. I know that it's possible to simulate an FPGA design in Altium but still have some simple questions: Would it be possible to simulate an FPGA with peripheral circuits? I mean another parts like digital ICs or (...)
No issue after I added a fa.vhd file to the design. You do know this is a very large combinational circuit. Using Vivado it ends up with >60 levels of logic (LUTs) from a_in to y. Of course I didn't add any constraints to try and improve the timing. e.g. 105366 Regards
sir,for what purpose we combine xilinx(vhdl/veilog) with matlab for particular image processing project. this is for speed or accuracy ?
can anyone pls help me how to design a double tail comparator in vhdl using modelsim software......actually im feeling very difficult in designing a each and every transistor in that double tail comparator circuit....
Hi, Register-transfer-level (RTL) abstraction is used in hardware description languages (HDLs) like Verilog and vhdl to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. design at the RTL level is typical practice in modern (...)
Hi, I am looking to design a parallel squarer circuit using vhdl and try optimizing interconnections to see if it can be more efiicient. The design template Im looking to follow is based on this
I want to get back to circuit design and decided to practice some of the problems. I'm using vhdl for coding. The problem looked simple to me, but to my surprise I was not able to solve it. Please bear in mind that it is not a homework problem. I work full time and simply want to do more of (...)
For clarity, you should tell about the synthesis tool and imported libraries.
Hi! I have done my Masters in Embedded Digital Systems from University of Sussex, United Kingdom. Passed out Sep 2012. My skill set include: FPGA design with vhdl, RTL design, synthesis and implementation ( have done a project in it), PCB design, Signal processing in MATLAB and Image (...)
Hi abdullah, tnx ,but I want to design a circuit and then simulate by Hspice.
Hi, I'm new to vhdl, but over the past two weeks I've been learning how to code using it, and was doing fairly well until I got stuck trying to do debouncing. I tried loops and even recursive functions until I found template code for debouncing in ISE (Xilinx). It seems to work somewhat, but my code is still giving me weird problems, (...)
Hi Dear all How can I calculate the maximum element of a NxN matrix? I know how to find it by matlab or C or even by using "for..loop" and "if" statements in vhdl but I am not sure that, Does this kind of coding synthesisable or not? ( I mean I didn't design a circuit for it before start to write the code). So what is your (...)
There's all sorts of avenues and some long-winded answers that could come off of your question... But personally I would say yes, aim to learn (in this order): (1) Digital circuit design (2) vhdl for digital circuit design and for testbenching (separate (...)
Logic gates (especially large scale) can be designed in vhdl (or Verilog) and then imported into Cadence for example. Cadence will allow you to simulate with these models. For transistor level design (e.g. one inverter), you can use Cadence and a control language (e.g. Eldo).
Not really that interesting, or that useful, and never a situation Ive ever seen anyone complain about. Afaik you cannot do it in any HDL (I dont think you can call half a function in C either!) If you think of the design using the simile of circuit components, how would you expect to connect half a chip on one board and (...)
I had installed FEL earlier. "Fedora Electronic Lab" targets mainly the Micro-Nano Electronic Engineering field. It introduces: * a collection of Perl modules to extend Verilog and vhdl support. * tools for Application-Specific Integrated circuit (ASIC) design Flow process. * extra standard cell libraries (...)
circuit design with vhdl by Volnei . Pedroni I have this book and at least my edition have a big problem. It uses the non-standard libraries std_logic_arith etc. There is no reason for a beginner to learn those libraries. First learn the numeric_std library, so it will become natural to you. It is (...)
first of all, you commented out the J and K inputs!
i have 3 questions 1-for the design of sequential circuit(mentioned at ch.8 in RTL book) it explain that the seq circuit is designed by (next_state logic , seq circuit and output logic). this design mean that the block is operate all time but only the output is (...)