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Hi guys! When i copy the layout of the triple well mosfet nfet33tw from the pdk (ibm 130nm) as it is and ran lvs on this single device without any modification or connections, the calibre is unable to recognize the device. Am i missing anything here? Thanks
Hi Everyone, I am struggling with using the Floorplanning tools in Layout XL to automatically place my IO cells. I have created a very simple schematic and layout cell in which I have instantiated 4 IOs - VDD, VSS, DVDD, and DVSS. The cells have been provided by ARM (...)
I was planning on upgrading my old laptop , from a pentium mmx to a pentium II, I have even bought the pentium II processor for it, But this is a weird issue for this Laptop, and i have no idea why ibm would do this, this laptop could come with a pentium mmx or a pentium II , this is where the issue, is (...)
I see nobody responding so I'll suggest that while you're waiting, you find a copy of the design kit docs and find the mask levels descriptions and groundrules that pertain to this layer. That ought to be what anybody who uses the process, would be regurgitating on your behalf.
Hi all i want ask about how I have access to design kits from TSMC, BSIM,ibm, and STM (65nm, 90nm, 0.13um, 0.18um)the aging model file.
Found another problem, my project uses functions deg2rad, angle, dB(S) in Qucs In QucsStudio deg2rad and angle gives "undefined/unknown function" error, while dB(S) seems give incorrect results.
We now have two problems that are related to temperature. Firstly, according to the BSIM4's model, we should have linear equation between threshold voltage and temperature, while when we simulate the NMOS, it shows totally linear, but in PMOS it shows some non-linearity. I wonder is this temperature non-linearity is caused by which (...)
Hi everyone, I am new on this forum and relatively new on analog design. I finished layout design of my low-voltage current mirror (100:1). I used 2D common centroid for better matching. After extraction spectre gave me Vth=335mV (346mV in schematic) for my unity MOSFET TN3. Everything else is same. What is mechanism behind this (...)
I tried to find the flatband voltage of the technology I use in the documentation of the technology (ibm 130nm) but it seems that this information is not provided -- is there a way to get the neceassary information somewhere (spice files)?
Hello, We have a design requirement for a Power PC based ASIC. Due to our existing relations with ASIC foundries, we can't directly license it from ibm/Global foundaries. Could you please suggest who can provide soft cores for PPC405 and its surrounding sub systems ( like PLB , OPB, EPB etc components) I have (...)
This link has a file with both the scan codes and ASCII values in hex for the keys on an ibm PC
Do you need to do that? Some foundries insist to do it in their CAD group, not trusting the dumb customer. See if any of the libraries (like the one with the pads in it) has a "scribe" or "die seal" PCell? No way would any foundry want you to free-hand it, there's a standard they want to (...)
Why don't you grep around in the PDK until you find these keywords, and then make sure the files they are found in, are in the include-chain?
Hi everyone, I am using ibm 130nm cmrf8sf PDK. I made a simple inverter and performed DRC, LVS, PEX with Calibre. The DRC and LVS work well, but there is a PEX error shown as follows: "error: Could not find pin mapping for terminal sub of cell (cmrf8sf devicepad symbol). (...)
hello, i'm new with analog design with this pack of ibm and i have a trouble that i can't solve. I'm doing a simple inverter with Mentor Graphics in this technology and in the schematic i put the subc for the NMOS, but i don't have a contact for the substrate of the PMOS, (...)
Has anyone used the process of LFOUNDRY in Germany ? How good is this company and is it stable ?
Hello, I've designed a digital core with ARM front end standard cell and an analog circuit in cadence Virtuoso in ibm 130nm. I wanted to do the mixed mode simulations in virtuoso. However, the ARM front end standard (...)
Hi, I am doing a layout of a simple common-centroid differential pair with multipliers and fingers using ibm 130nm cmrf8sf. DRC runs fine. But i get malformed device error: *ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device. Any ideas on how to solve this? Thanks.
You should characterize your devices before using them. Run the id vs vds curves for a bunch of different W and L. Find out how lambda varies.
Hi All I am familiar that MIM cap can be placed on SUB or NW. In ibm 0.18 they give a third option for the backplate, which is BB layer. Does anybody know what is this BB layer used for and any pros and cons? Thanks!