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First, can you understand difference between idt() and idtmod() ? Second, can you understand arguments of idt() and idtmod() ?
Hi All, In the attached frequency locked loop, why is there a need of compensation network formed by Rz,Cz, and Cc? As far as I see there is only one integrator in the closed loop, the OTA. The oscillator from vctrl to output frequency is just a gain block since the output variable of interest is just frequency. Single integrator loops (...)
Hello there, I have an image processing design developed in Xiinx system generator and i have exported it as an IP core. But i have problems in sending and receiving image data in SDK. Does anyone work on these lines.? so that i can ask you further..
Hello everyone, This is my first post in I have an example design in system generator for image operation which has one input and one output. I want send data through AXI stream interface and export it as an IP core to vivado IP integrator and develop the design further using DMA and (...)
Hello, I have designed an integrator with 15 M resistance and 40 PF. The input is a single pulse with a width of 409Us and higher value is 700 mv and lower value is 100mv. The deintegration curve is exponential. How to make it linear?
Check out periodic steady state analysis (pss) and periodic ac analysis. They're very convenient as they work the same way as regular transient and ac simulations but instead of using DC operating points they use periodically changing operating points (the charge and discharge phases in SC integrator). You can find many (...)
Hello folks, Can anybody help me to calculate the input capacitance of a SC integrator?? what be the parameters to determine the capacitance needed to design the integrators? (specially input and output caps.)
That's a lousy test method for such a detailed question. You embed time-domain low-overdrive errors relative to a DC Vio spec / interest. Testing of real comparators tends to put them in an integrator / divider loop which gives you a high gain measurement point and gives the comparator a quiet low impedance drive at the inputs.
Hi, Consider the following two circuits, being an integrator with identical component values (R, C, OpAmp impedances, gain, ...) in its single-ended and fully differential version (the amplifier is a behavioral model basically just a VCVS): 132932 Ignoring the nonlinear resistance in the circuit and I confirm with t
Hi, I need help to determine the op amp gain required to match certain ADC specifications. I need to design a delta sigma 14 bit ADC and need to find out required op-amp gain for the integrator design. Is there any certain formula to find out that
Hi, We are getting the current from Charge pump and then we converted it into voltage and the again into current. What is the use of this procedure. Are there any advantages. Normally a digital PLL has a phase comparator and an integrator with lead/lag compensation RC network to drive the VCO. Using a charge pump
hi all, can anyone help me explaining, how charge balance method can be used to measure pressure from a differential capacitance pressure sensor. I want to know if a 74hc4052 can be used as an integrator? I want to connect a differential capacitance pressure sensor on the input channels of the multiplexer(74
131459 From this figure, the red signal is original pulse and the others(blue signal) is integrated result. As you can see, there are an oscillation in the integrated graph I used RC integrator which is its work band almost cover spectrum of original pulse (11-70MHz). My advisor told me, "I used impro
Hi, i want to realize a fully digital closed loop pwm modulator for my class d amplifier but i've no idea on how to start with my design. Googling i've found sigma delta modulator and self-oscillating class d amplifier implemented in analog way (input+feedback -> integrator -> comparator -> flip-flop). At the moment the mosfets of my class d
Yes you can. With that curve - and if the frequency doesn't vary too much, you can use an opamp integrator and a SR latch - one input inverted so you don't need two sets of integrators. You most expect use some time to tune the RC value so that the rise curve doesn't get the output of the integrator high (...)
As the figure shows, do the noise simulation, but the output and negative input node of the amplifier is not "directly" biased, how to get the input referred noise data from simulation? Thanks 129361
I need an integrator that will handle +100v output. This is a serious problem due to the lack of high voltage opamps. It's my understanding that integrators need to be unity gain stable. Would this opamp work? It seems to show unity gain capability under the "gain and compensatio
Your request is unclear. 12 to 0 >>> 0 to 5V inverts the non-inverting integrator. Pls clarify and the requirements for clamping the output, as well as not exceeding the input common mode range of the Op Amp with a reduced Vcc.
Put it inside the classic op amp measurement loop, let it chatter and look for 50% duty (via the integrator threshold). That's how we did it and I believe how it still gets done, on production ATE. Open loop DC or triangle wave stimulus can get you close but not any decent accuracy / repeatability.
The feedback from the resistor allows the output of the first integrator to be a bandpass and the value of feedback resistor allows adjustment of the Q.