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Hi, I am trying to import pspice .cir file into cadence spectre and I have successively generated the schematic graph. However, when I run the simulation, some errors appear. Here are the errors 157880 Here are the settings in schematic 15788115788215
I am trying to replicate a 4 X 4 butler matrix How should I emulate the MIMO encoder and decoder in Sonnet
157893 I have solved the circuit and calculate Q point. Very simple and easy. But my answers don't match with multisim DC OP analysis. According to my calculations VCE = 2.2V IC = 5.2mA With multisim the results are totally different. VCE = 4.6V IC = 5.3mA Where is the problem?
Hi, In most cases fc = 1 / ( 2 Pi R x C) applies. R3, R4 act as a voltage divider, thus for C2 2.55k applies. Choose fc to be very low, much lower than 10Hz. C3 should be tge same as C7, with 470k as resistor for fc calculation. Fc should be lower than 10Hz. C4 and R8 determine the upper cutoff freqyency of the signal. The same ap
I have silver solder in wire form. It's stronger than normal tin/lead solder. Silver type is useful to fix metal parts where the fix should be done quickly and occupy a small area. The aim is to avoid generating excess heat which discolors adjacent metal. Example, eyeglass frames, jewelry. I keep a separate soldering iron which I use only for t
Hi all, After reading some threats in the forum, I couldn't find an answer to my question - I am using a TSMC 130nm RF spice model and trying to simulate mismatch in Cadence ADXL with MonteCarlo analysis, with no luck. I was able to simulate corners with no problem (SS,FF,TT,SF,FS) but when choosing a MonteCarlo corner (or at least thinking I am
i 'm facing the problem of uc3843/3842 VCC in a uc3843 based smps that show Vcc about 86vdc or even greater when the power mosfet & ic is not in the circuit. but when i place the ic, the voltage through kick resistor drop to 6.5v. the kick resistance value is 150k/2w. i blow up three 13n50 mosfets today beca
when we say an antenna has an impedance of 50 ohms, that means the antenna is connected to a load of 50 ohms and the load is not part of the antenna?
In this case ".elf" is generated for a arc processor from a synopsys metaware IDE SDK tool. I want to convert to .bin or particularly .hex file so that i can use it for a verilog memory initialization file ($readmemh) and do some simulations. Thanks
hello, this printer power supply is dead,I cant figure out with my limited knowledge that why the lower output part of circuit is not getting any DCV. I have measured voltages across transformer and I found 24v but nothing on the other side of transformer, please have a look at pictures, any help is kindly appreciated. thanks. [COLOR="#FF00
I am attempting to recreate and reproduce the work of a researcher, in HFSS, on a dual and quad output switch, and would like some insights into how to implement the boundary conditions and excitations respectively. I have an attached an image of the device. The distances between the central beam and input (...)
I am attempting to recreate and reproduce the work of a researcher, in HFSS, on a dual and quad output switch, and would like some insights into how to implement the boundary conditions and excitations respectively. I have an attached an image of the device. The distances between the central beam and input (...)
i know that it is not possible to draw meander line helix in CST. how shall i draw parameterized meanderline helix to be imported to CST for simulation and optimization? Please refer to the attachment for the example of meander line helix.
I would like to know the RF circuit implementation method for 20GHz to 40GHz. The RF circuits are LNA, filters and PAs. Can these circuits implemented on a PCB or only IC? Any particular IC technology needed?
hello, this printer power supply is dead,I cant figure out with my limited knowledge that why the lower output part of circuit is not getting any DCV. I have measured voltages across transformer and I found 24v but nothing on the other side of transformer, please have a look at pictures, any help is kindly appreciated. thanks. https://i.i
I've finally bitten the bullet and crossed over from VHDL to the dark world of System Verilog. I've got a testbench that causes Questasim (Modelsim) to throw the following error: # ** Error: (vlog-13069) C:/AirMattress/ARIN_Main/tb_top_beam.sv(571): near "[": syntax error, unexpected '[', expecting ';'. Here's the piece of code that causes th
Hi All, I am trying to improve the thermal path for the DFN-8 package and I wonder what kind of options do I have?. Can I just moves tracks around and and fill the area with copper, Could I put plated vias for better thermal management?. Thanks, Winsu
Hi All, I have come across with this regulator and it just specifies the max thermal junction. I can just get temperature from the case, how could I calculate the max temperature possible on the case if I don't have the thermal resistance between junction and case?.
Hi, I need to implement 1 GigE with either FPGA or ZYNQ. I am wondering performance wise which Ethernet option is more promising. 1- FPGA with external Ethernet Microcontroller (MAC and PHY) on external chip 2- ZYNQ 7020 having MAC inside the chip but it need external PHY
Hi All, I have to glue a heat sink on a chip which is getting super hot. The dimension are width 6.3mm and length. Anyone could recommend something to glue it?. I have though in thermal tape but it wont secure the heat sink enough... Thanks, Winsu