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Hi, In the Vicor DCM3623 DCDC module datasheet (below) , page 21, there is, at Figure 23, an LC input filter to some DCM3623 modules in parallel. Each Inductor of this LC filter has a 0.3 Ohm resistor across it. The Capacitors (?C1_x?) are all ceramic capacitors. Do you agree that the 0.3 ohm resistor across the filter inductor is basically t
It looks as though mains AC comes in at left. and I think it filters power to an appliance at right. I'm reminded of a store-bought 'noise filter' which I took apart. It claimed to improve radio and tv reception as well as reduce hum coming through my audio equipment. Inside I found a capacitor and coil of fine wire. Not too complicated. (...)
I am trying to read an assertion signal from a fsdb file using fsdbReader library. As given in the Fsdb Reader document, I used ffrObject::ffrAddToSignalList( fsdbVarIdCode) and ffrObject::ffrLoadSignals to load the varId But it throws error /************************************ *WARN* Failed to load
I want to model a complete PLL behaviourally and use MATLAB with an arbitrary VCO phase noise profile. My VCO has a known KVCO and a known Phase Noise at a 1MHz offset (say 130dbc/hz). I also know the VCO noise floor (say -140dbc/hz) and that it has a 1/f^3 dependence elsewhere. How would I model this VCO in MATLAB for a (...)
Hello , i want to implement the example of simple common source amlifier shown bellow. I have constructed Id/(W/L) as a function of gm_id. we calculated in the example that gm/id=14 which in my plot i got Id/(W/L)=7.7uA i Have W already when i created the plots so i have all the data when i created the plots.I dont know what do i input int
Briefly..pick a ferrite core (eg ETD, PM, POT core, etc etc)....see eg ferroxcube or TDK data books of cores. Then you will wind it with enammelled copper wire to your required inductance...or rather, use Litz wire, such as TEX-ELZ by furukawa (skin effect) Check your saturation current with Isat = BAN/L B = 0.3T A = core min cross sect. area N =
Hi! I am using W5300 module and initialing it on TCP mode with Spartan6(FPGA). I can open the socket in TCP mode, and I also can establish it. When I send data to it and read the RX_FIFOR, I just cant read the number of data has been received . I create a loop for buffering data, but I can not read them. What is the problem?
Hi all. Looking for a programmable receiver ( IC?), that can work on 3V to 5V for the VHF band. Seen many ICs in the market; mostly for broadcast FM 3 metre band and for 433MHz, that without disclosing it openly in their data sheets, may perform between 100 and 200 MHz. TV tuning ICs too, for the VHF (...)
Hi All, Anyone has got experience using EASYPCB ?. I need to get step files or something similar that can be export from an EASYPCB file to solidworks and shows all the relevant dimensions for mechanical engineers such as dimensions of the board, width, length and height of every component and dimension of holes...etc.
Hi there, I wanted to know how to actually implement the P, I and D sections of of controllers in hardware? What is the actual electronic circuitry behind it? If possible pls. point me to a relevant textbook as well. Thanks and Regards, Arvind Gupta
I have PIC16F886 4mhz crystal 1ms timer interrupt.I have code working as below. Now currently facing updating ms and Sec parameter. the min and sec parameter will update properly but not in msec and sec void interrupt isr(void) { asm("clrwdt"); if (TMR1IF) { TMR1IF = 0; // TMR1H = 0x3C; // TMR1L
Hi, Gurus, Attachment is one MTBF picture searched in the Chinese webpage. There is an example in the picture: Say confidence=90%, and MTBF=300 hours, and failure number is 3, then T=0.5*(X0.9(2*3+2))^2*300=524 hours. Here what confused me is how can they calculated 524 hours? What does X mean? Integration? Best, Tony Liu
In two-tone nonlinear simulation. How much should be Fspacing? and also is it RF frequency should be the centre frequency? Note: my target frequency band 3.4-3.6 GHz. thanks
We are a midsize biotech organization with little/no internal Si design expertise that is likely to need outside design services for low-noise transimpedance amplifier arrays: 1000s of channels (possibly 10k's of channels in subsequent revs of the design), on as tight a pitch as reasonably possible. This will be Si-level design, with integrated D
I'm trying to figure out why when I measure current on my FLUKE 289 meter it reads .536 on the mA scale and 276 on the uA scale when I apply .52v from a power supply through a resistor. I assume the difference internal resistance. Can anyone confirm? Thanks PV
Hello, I have a HP laptop (model: 15-ay013dx) with 6GB RAM installed in it. I wanted to upgrade it to 16GB. So, I bought two 8GB DDR4 RAMs. However, after I replaced both of the pre-installed RAMs on my laptop, it isn't starting up (CAPS lock blinks). But when I replaced one previous RAM with one of the new RAMs and kept another old RAM then it
Hello, I have designed simple voltage devider MOS resistor, the circuit is working fine in schematic, with the layout there is no issue, LVS is giving o error. However, in the simulation they are showing very different result, then when I compared the netlist I saw it is different between the schematic and layout, looks like he is mixing between
I am having 14 bit ADC data which is in 2's complement format. I require to convert in 5 bit format using vhdl language. What is the easiest way of doing it apart from using if then else statements comparing magnitude? Consider the input data to be in two cases unsigned and signed.
I need to measure the relative phase of two sinusoids (around 2-2.2MHz. Both signal are always of identical frequency) using an FPGA. Both signals are sampled with an ADC at 40Msps. Everything about those two signals is synchronous to that sampling clock. Getting a phase measurement which is both accurate (like <5 degrees) and also gives unique res
Hello, it comes into my mind such idea: extend AVR Soft-Core described in this new inst