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Hi, I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz. I had read about using rising and falling edge detectors but they fail to give 50% duty cycle. can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency?? what are the othe
like XC or some other C ProgrammerThere is the ESP-IDF toolset available that compiles in C++, however since its is not very friendly to deal even with simple applications, it is recommended only for those who are familiar with low level of programming to interface with its hardware modules. Only in the specific case of Espressif ES
Your ex0_isr_counter should be of int type and the new code should be write_byte_to_eeprom(0 , (ex0_isr_counter & 0xFF)); write_byte_to_eeprom(1 , ((ex0_isr_counter & 0xFF00) >> 8)); display(ex0_isr_counter);
Hi, Is this the ?cheap, quick and easy way? to do high power SMPS?s? The attached shows two identical Two Transistor forward converters in parallel?..each is 1.2Kw (50vout and 24iout) If any one trys to hog all the current?its current limiter kicks in and stops it from doing so. Many more can be similarly paralleled to build up a (...)
Hi everyone, I try to get the jitter from a clock generator, but I also need the phase noise curve for other reasons: - When I simulate my circuit with the pnoise/jitter method, I get a RMS Jitter in a given bandwidth of 594.386fs (Jee>RMS). - and when I simulate with the pnoise/time average method, by calculating my Jitter from the Phase Noise
Hi, We are doing a Test PCB containing one Vicor BCM4414xH0E5035yzz module, which will feed 4 paralleled Vicor DCM3623x50M53C2yzz modules. (these are all DCDC modules) The BCM module will dissipate 84W. Each DCM module will dissipate 43W. We are going to need heatsinks on them. We think the best way would be to put 3mm NPT holes near the 4
Hi everyone, I try to get the jitter from a clock generator, but I also need the phase noise curve for other reasons: - When I simulate my circuit with the pnoise/jitter method, I get a RMS Jitter in a given bandwidth of 594.386fs (Jee>RMS). - and when I simulate with the pnoise/time average method, by calculating my Jitter from the Phase Noise
Dear friends, I see most of the designers makes the PMOS transistor three times bigger than NMOS (to compensate for mobility difference) when designing the TG, what this lead in actual circuit performance, while Ron(tG) = RN||RP, it means if the target to reduce RON then we can make NMOS=PMOS and increase them both, what is the advantagues of
I'm a bit baffled because the diagram doesn't show a ground. Getting the antenna to resonate is different than getting the antenna to radiate. You can have a nice S11 and the radiation have '0-1%' efficiency. There must have been assumptions made. Generally speaking, it's all current flow and field termination. The ground areas where the curr
Sounds like you'll have to interpret the active behavior from the datasheet and set each parasitic variable in the SPICE model manually. It's a trial/test process.
Hi there, I am trying for days to simulate a simple antenna design with Ansys HFSS and I am always getting this error message: === Ansys_MapleWireless5300_2 (C:/temp/Ansys_MapleWireless5300_2/) HFSSDesign1 (DrivenModal) Solving adaptive frequency ..., process hf3d error: Failed to solve port 1, solving at too low frequency is a
Hello all, 157732 I am trying to find a solution to stop my measurement setup from drawing power if the ucontroller losses power, or the computer controlling the setup reboots. Putting aside a lot of the details: I have an arduino based ucontroller controlling a stepper motor control board. The arduino is powered by th
The price is decisive. Pressure of 1 kPa barely moves the needle on an everyday automotive vacuum gauge. This low pressure might be detected by the depth of liquid a hose is immersed and still allow gas to flow. The liquid should be chosen so no harm is done if it contaminates the gas. Flow rate is indicated by th
Which of the following is a type of error associated with digital-to-analog converters (DACs)?
Hi , At the moment I am trying to perform parasitic extraction using PVS-Quantus to get the RLC parasitics of the metal stack (routing). the Pcell of my the transistor already includes RLC parasitics , I want this part of the layout to be blocked from parasitic extraction to avoid parasitics double counting To do that : ? I preserved the
Hi, I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz. I had read about using rising and falling edge detectors but they fail to give 50% duty cycle. can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency?? what are the othe
Hello. I am working on a project to improve wifi strength of an android tv box in a classroom. It comes with a 50 ohm dipole antenna. In the classroom, the router or repeater is situated in the rear of the classroom. I proposed replacing the antenna with a transmission line fed patch antenna. Simulation indicates 7.14dBi directional gain compare to
How to build a HFSS model to solve the following problem: there is a two-wire transmission line: 157726 The line incident uniform plane wave has a frequency of 100 MHz and is traveling in the xy plane in the y direction, and is said to be incident ?broadside? to the line. It is required to find the voltages Vs and Vl at t
I have bluetooth transceiver operating from 2.4G to 2.48G with 79 channels with 1MHz width and 1MHz spacing. I want to receive Channel 2 in the Receiver. What do I sent the LO frequency to be in a heterodyne receiver to capture this Channel 2 ? Is is the center of the second channel at 2.404 GHz (edge) or 2.4045 (center of channel) ?
Say I have inputs as follows: input in0; input in1; input in2; input in3; ... and what I want to do in generate for loop is something like this. b = in0; b = in1; b = in2; ... and so on. The problem is I cant index the inputs using the variable 'i' in the generate for loop. How can I do this e


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