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Can I use the following to find out the internal source resistance of the signal generator? I use a DC voltage source driving the signal generantor and 10K ohm resistor in series. Base on the current and voltage drop across the 10K ohm then I can find out how much the source resistance of the signal
Hi i have a parallel 16bit nor flash device implemented in a project unfortunately it is getting obsolete. I want to replace it with a similar device. I don't know much information about the code currently running on the board. While comparing the nearest part i could find, i understand that the page size for each is o JS28F128M29EWHF
I am synthesizing a cholesky decomposition algorithm using verilog and synopsys DC. I've also written a customized cell library, which contains the following cell: and OR XOR IV Nand nor Xnor DFF MUX It was sufficient for me to compile functions like Division and Sqrt.
Although you can use two uncoupled single ended transmission lines for differential signals, that's neither the usual nor a practical way. Consider that the effective differential impedance is formed by the parallel circuit of differential (wire-to-wire) and single ended (wire-to-ground) components. In PCB design, space saving demands to (...)
i write this code, a pulse with period 300ms. then it delay 200ms.What pulse do you want to generate ? You specify neither duty nor pulse widthes for high and low. Describe correctly with using correct terminologies.
didn't work on a breadboard at 2Hz, 3, 16, 32, 64, etc., up to 16.7kHz, and changing passive components to fit frequencies, until I connected the nor gates as inverters See how this compares to an led chaser I experimented with in hardware recently. It has output pulses overlapping, like your diagram. Counter to normal
Hi, I'm using orcad capture CIS for schematic design, when i move or drag components or part name it shows warning due to that i'm not able to arrange the components properly. But i can able to move by cut and paste. Kindly give a suggestion to solve the issue by any settings. h
I can able to design Full adder and Full Subtractor using 12 nor gates. But I want to realize Full adder and Full subtractor by using Minimum number of nor gates i.e 9 nor gates. Please explain this Realization
You are driving CART1_B and CART2_B by the instance LC_CAL and the process, you commented out the assignments in the reset branch but left the assignments in later branches.
Give me an idea to solve thisI am really puzzled trying to understand how someone expect to have some help without posting any code nor schematic diagram.
Hi I got cadence IC616 and MMSIM13 from and installed it successfully and also applyed the patch successfully but it does not have license.dat file neither in IC616/share/license nor in MMSIM13/share/license I request you pls share the license file or email me
other objects such as a meterstick (held from a long distance), scissors, or a pencil also create the same effect. Also, the circuit also randomly inverts (sometimes it gets brighter the closer we get, sometimes it inverts and becomes dimmer the closer we get). Your question has been already answered in post #4 and post #5. Co
The answer is simple and can be given by thinking quite a bit. Full duplex is only possible with separate communication channels for RX and TX, as e.g. RS-232 has it. Neither LIN (single line) nor CAN (single differential pair) does provide it.
Some gates invert their output. A dual input "OR" gate like a CD4071: with either or both inputs high, the output will be high. A dual input "nor" gate like a CD4001: with either or both inputs high, the output will be low. The difference is the nor inverts the output. There are also and and Nand gates. You (...)
As you don't show the code for interfacing to the ram nor do you have enough code to attempt a simulation and you didn't zoom in on the waveform (can't even see where the clock transitions occur due to "aliasing" of the image). I can only guess you aren't handling/understanding that the ram is synchronous (i.e. has registers (...)
Hello, This datasheet is extremely slow to respond to scroll up and down commands, do you know why?
The firs thing that comes to mind is two nor gates in the same arrangement as done with an SR flip-flop to store trigger commands. Had you already performed some mental simulation with that kind of circuit ?
There isn't any model for such circuits for neither ADS nor any.Its' characteristics are defined and you take it, use it.
I have used a NPN power transistor (BD137) plus a 270Ω resistor and a 5V zener to make a regulator which gives me a 4.4V output which is still too high. BD137 isn't suited for 2A load, neither in terms of rated current nor power disspation.
1. Difference between qualitative and quantitive analysis? If we want to perform these for any electronics circuit qualitative: data are not calculated nor simulated nor measured; they are estimated - at best; quantitative analysis: data are calculated, simulated or measured. [QUOTE
There looks to be no activity and I also see no power supplies nor ground, which might be why? Even what should be stimuli (a, b, cin) seem to be doing nothing. Your output plot lacks any info that might let us check whether output is correct for the input state (levels). I'd start with drilling into one of the gates and see if it's (...)
It's most likely an estimate based on the SDC constraints for the clock and a 12.5% toggle rate of all FFs that use that clock. It's therefore likely to be very inaccurate, probably in excess of +/-30% off. FPGA dynamic power analysis tools for both Altera and Xilinx do exactly this type of calculation and report that the results have very (...)
If you don't care about performance then you can build your clock tree out of whatever you like. But if you care about edge dV/dt symmetry and transition time (you might, if you're pushing technology performance) or layout compactness or power dissipation, then any more baggage or lesser / asymmetric drive strength will not help. That is to say,
hi everybody, i am trying to interface jhd162A lcd with pic18F25k22 microcontroller. Port A is used to connect lcd control as well as data lines. Initially i used port registers to write outputs but after reading through the forum i changed it to Lat . i am using internal oscillator INTOSC67 in config1 register as clock thus i
Have someone ever used the LT3650? I have designed a circuit charging a 18650 battery. It works ok but the IC gets very hot (50C) at 12V input and over 65C at 28V. The IC has about 20mm? of copper on the bottom side and about 10mm? on the top side. Charging current is set to 1.5A. IC should have thermal shutdown but is this heating (...)
Hi, Anyone knows how to build a or/and/nor gate with VCVS in Hspice commond line( Hspice code)? The syntax is : Multi-Input Gates Exxx n+ n- gatetype(k) in1+ in1- ... ink+ ink- + x1,y1 ... x100,y100 But can anyone give me an example of two input OR gate? Y=A OR B. I d
Hello every one I have a project with PIC18F97J60 because of the ethernet communication capability in it, but I didn't found it in ISIS proteus and in microC for PIC also how can I add it to them, thank you.
I do not believe that you can sweep a component value with the AC Analysis in LTSpice Read about .STEP command
I was working on my project with logic, sequential and combinational ICs. and, wanted to test the 74LS10 3-input Nand gate and it wasn't working!! All other ICs are working, nor, 2-input Nand, counter, 555 timer. I've other 74LS10, if they all not working then I'd combine 2-input (...)
Hello, I need to interface a shared SRAM on Zynq FPGA . I saw in ug 585 manual and found that there are dedicated parallel SRAM/nor flash pins in the PS for SRAM interface. Alongside with this SRAM, I need to interface a QSPI nor flash. The problem is that few pins of the MIO are overlapping between the parallel SRAM and (...)
Pretty sad that I am asking this when I took E&M as a physics major 3 years ago. "When a conductive wire is in a magnetic field, current is induced" Right hand rule, point your thumb in the direction of the current, magnetic field around wire.Or is it simply orthogonal to the wire? Anyway... When you take rotational motion from an outside so
Does the microcontroller output varies only between high and low? ex. high means 5V and low means 0V? Thanks in advance..
That has to be the most complicated and convoluted keypad code ever written. Make life easy for yourself, put the rows on adjacent pins and the columns on adjacent pins, then use the shift operators to scan the keys. Brian.
Why would anybody want to simulate an LED that has three different LEDs in it? A school kid? Simply buy one that has an English datasheet and make a circuit for its spec's. Look at its ranges of forward voltages for its three LEDs. If all three colors are lighted (lit?) then observe its maximum heating rating.
Initially I would be tempted to define the maximum operating frequency by the critical path, as being the propagation time of each one of the three nor gates, added to the propagation time of the and gate. However, as there is a symmetry in the circuit, in theory one side should balance the delay of the other, but I believe that the maximum frequ
You would just need a toggle Flip Flop, a one shot and two active low switches with Relay coil common to V+. Single push button goes to one shot which debounces push button and drives FF Clock input in /2 mode or toggle mode ( D=Qbar) Q and one shot = Gate drive 1 Qnot nor one shot = Gate drive 2 FETs would be N (...)
Q1-3: The circuit doesn't correspond to a clean toplogy, it has two feedback pathes and is neither clearly CB nor CE. Don't expect simple answers. Q4: Quiescent current is related to transmitter range. C945 has however a wide range of current gain, so actually achieved transistor current can be quite different. Suggest to try yourself by varying t
while design a nor3A ie a 3 input nor with A input inverted. we have two ways build a two stage nor3A OR build a 3 stage and3BC(apply demorgans to nor3A ) so while computing the delays i found that 3 stage design was faster. so i got a question here is that how is it faster? and what (...)
while design a nor3A ie a 3 input nor with A input inverted. we have two ways build a two stage nor3A OR build a 3 stage and3BC(apply demorgans to nor3A ) so while computing the delays i found that 3 stage design was faster. so i got a question here is that how is it faster? and what (...)
Hi, we can neither check your hardware nor check your code, as long as you don´t post it. So I´ve googled and found a lot of "how to use GY80" guidelines. Did you read them? Please provide more information. Klaus
Put a 3V bulb or a white LED or an appropriate resistor between the 15 volt power supply and the relay coil. The COM pin probably has the better thermal conductivity to the relay coil.
you do not tell us how long the interconnecting transmission line is, nor how much amplitude ripple you can live with over a bandwidth. If they are really close, just hook one to the other. If they are far apart, you could add a series resistor at the mixer, and run 75 ohm line. if it is narrowband, you could just (...)
Not knowing your technology nor your DRC rules, I 'd assume: You have N_WELLs WITH DIFFERENT POTENTIAL in your layout. Seems - in your technology - that N-Wells have to be marked (e.g.) by a DNW_LV_MARK marking layer. But there must be different DNW_LV_MARK marking layer polygons for N_WELLs WITH DIFFERENT POTENTIAL. and these have
you don't say it is video or stills nor if it color or B/W nor resolution BUT if you need to do 1) and especially 3) as well you definitely can NOT use a wee micro-controller, you need a full-blown PC.
Hi guys, 1. I'm simulating 8 bit mips processor from CMOS VLSI DESIGN: 4th Edition. This is results that I obtained for Astro and VCS using Synopsys. I've no problem with Astro but for VCS simulation, at the first instruction, the result is ok but when it proceeds to second instruction, there is something which I not quite understand. Why the me
* If LiPo has I*t= 5.5Ah then energy storage is V* I*t = 25.9V*5.5Ah = 142Wh > x3600= 511,200 W-s= Joules By comparison your 9V primary battery is only 9V *0.6Ah *3600s/h =19,440 Joules Thus your LiPo ( ignoring charger type inefficiency ) will take 511,200/19,440=26 times longer charge time with 26x more energy st
Hi, I need some help. I have an HP8565A and I have no Frequency readout neither on the CRT nor on the LED readout. The problem started a few months ago when the LED readout started to flicker and display intermittent lighting of the segments. Now it just displays 0.0000 I checked the 10V reference and is within (...)
See the 74HC14 datsheet circuit. Essentially the inverters of the basic FF are replaced by Nand and nor gates.
I do not hold solder in my teeth nor with my toes. instead I fasten down the item I am soldering and hold the solder in one hand and the soldering iron in the other hand, or I fasten down the solder and hold the item to be soldered in one hand and the (...)
Your photo-diode is not a current nor a voltage source because it is reverse biased. Then light on it causes it to leak and become a resistance. Then it conducts some of its bias to the opamp input. A photo diode without bias is a tiny solar cell that does generate a voltage and a current.