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460 Threads found on edaboard.com: And Nor
The loop is a bit misdrawn, and the scheme would require you to know the generator's internal voltage amplitude or the 10K resistor's current (which is not shown to be measured, nor the added series resistance of doing that). If your signal generator is the normal 50 ohms then what you measure at the 10Kohm resistor owes more to the (...)
Page structure of parallel flash is only relevant for erase and write. Data is simply read word-wise.
I am synthesizing a cholesky decomposition algorithm using verilog and synopsys DC. I've also written a customized cell library, which contains the following cell: and OR XOR IV Nand nor Xnor DFF MUX It was sufficient for me to compile functions like Division and Sqrt.
Although you can use two uncoupled single ended transmission lines for differential signals, that's neither the usual nor a practical way. Consider that the effective differential impedance is formed by the parallel circuit of differential (wire-to-wire) and single ended (wire-to-ground) components. In PCB design, space saving demands to (...)
i write this code, a pulse with period 300ms. then it delay 200ms.What pulse do you want to generate ? You specify neither duty nor pulse widthes for high and low. Describe correctly with using correct terminologies.
didn't work on a breadboard at 2Hz, 3, 16, 32, 64, etc., up to 16.7kHz, and changing passive components to fit frequencies, until I connected the nor gates as inverters See how this compares to an led chaser I experimented with in hardware recently. It has output pulses overlapping, like your diagram. Counter to normal
Hi, I'm using orcad capture CIS for schematic design, when i move or drag components or part name it shows warning due to that i'm not able to arrange the components properly. But i can able to move by cut and paste. Kindly give a suggestion to solve the issue by any settings. h
I can able to design Full adder and Full Subtractor using 12 nor gates. But I want to realize Full adder and Full subtractor by using Minimum number of nor gates i.e 9 nor gates. Please explain this Realization
You are driving CART1_B and CART2_B by the instance LC_CAL and the process, you commented out the assignments in the reset branch but left the assignments in later branches.
Give me an idea to solve thisI am really puzzled trying to understand how someone expect to have some help without posting any code nor schematic diagram.
Hi I got cadence IC616 and MMSIM13 from and installed it successfully and also applyed the patch successfully but it does not have license.dat file neither in IC616/share/license nor in MMSIM13/share/license I request you pls share the license file or email me
other objects such as a meterstick (held from a long distance), scissors, or a pencil also create the same effect. Also, the circuit also randomly inverts (sometimes it gets brighter the closer we get, sometimes it inverts and becomes dimmer the closer we get). Your question has been already answered in post #4 and post #5. Co
The answer is simple and can be given by thinking quite a bit. Full duplex is only possible with separate communication channels for RX and TX, as e.g. RS-232 has it. Neither LIN (single line) nor CAN (single differential pair) does provide it.
Some gates invert their output. A dual input "OR" gate like a CD4071: with either or both inputs high, the output will be high. A dual input "nor" gate like a CD4001: with either or both inputs high, the output will be low. The difference is the nor inverts the output. There are also and and Nand gates. You (...)
As you don't show the code for interfacing to the ram nor do you have enough code to attempt a simulation and you didn't zoom in on the waveform (can't even see where the clock transitions occur due to "aliasing" of the image). I can only guess you aren't handling/understanding that the ram is synchronous (i.e. has registers (...)
Hello, This datasheet is extremely slow to respond to scroll up and down commands, do you know why?
The firs thing that comes to mind is two nor gates in the same arrangement as done with an SR flip-flop to store trigger commands. Had you already performed some mental simulation with that kind of circuit ?
There isn't any model for such circuits for neither ADS nor any.Its' characteristics are defined and you take it, use it.
I have used a NPN power transistor (BD137) plus a 270Ω resistor and a 5V zener to make a regulator which gives me a 4.4V output which is still too high. BD137 isn't suited for 2A load, neither in terms of rated current nor power disspation.
1. Difference between qualitative and quantitive analysis? If we want to perform these for any electronics circuit qualitative: data are not calculated nor simulated nor measured; they are estimated - at best; quantitative analysis: data are calculated, simulated or measured. [QUOTE