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130 Threads found on And Using Mux
I am synthesizing a cholesky decomposition algorithm using verilog and synopsys DC. I've also written a customized cell library, which contains the following cell: and OR XOR IV Nand NOR XNOR DFF mux It was sufficient for me to compile functions like Division and Sqrt.
you should probably describe the circuit connection between the camera (also give the camera part number) and the TW2837. I suspect you've got something connected wrong or are missing something in the way you are connecting them.
Hi all! I have design with clock multiplexers and clock gating cells. I'm using Cadence RC compiler for synthesis. After synthesis, i need to simulate resulting netlist with SDF file using ncsim. When i run the simulation, i see that clock mux and gating cell delays are not '0'. How to get an SDF file with (...)
For (0,1) I get that 1st TG is open and the 2nd TG is closed. Didn't you note that the 2nd pair is driven by S'0, but not S0 ?
I'm trying to understand how 4:1 mux using TGLs works. This is the example which I'm looking at 133499 I've understood how 2:1 mux works but I don't get how 4:1 works. For input1, I understand: for (0,0) both pmos-es get 0 and both nmos-es get 1, so they're both open => the out is (...)
Hi! I am trying to model an Arbiter PUF in Hspice. You can google it if you don't know what that is. So I am trying to implement the delay differences in the multiplexers due to process variations. In order to do that I have to run monte carlo simulations using hspice and vary the oxide thickness and the threshold voltage of the (...)
Hi all! I want my Raspberry pi to access internet as well as to be able to receive and make phone calls. To do so, I have a sim900 shield like this one Itead Studio sim 900 v1.1 . I connect it to my Raspberry using GND and 5V and TX RX from serial port. I followed
Hi, I have the logic that generate DDR output signal e.g. assign DDR_out = clk ? DDR_pos_reg : DDR_neg_reg and using DC to synthesis it. clk signal is the select of the mux and create data value on both edge. This architecture is valid as mentioned in thread. But I checked the clock tree log fi
Here are my process statements for a 4:1 mux using 'if-elsif' and 'case' statements in VHDL. process (A,B,C,D,sel) begin if (sel = "00") then Y <= A; elsif (sel = "01") then Y <= B; elsif (sel = "10") then Y <= C; else Y <= D; end if;
Hi All, I am new to the frontend. My expertise lies mostly in the back end . I am trying my hand at verilog coding and simulations using ncvim. Some how I a not able to dump a proper vcd file to view in simvision. Can someone please help me to figure out the issue. This is the content of a simple mux ( file (...)
I've got a device I need to connect to multiple power supplies and a controller for testing. The device has several modules that all operate off different voltages (12V, 24V and 48V). The device under test (DUT) has a housing that is used as a common ground point, with all the supplies and controllers connected to it in a (...)
Hi, I am using RTL compiler to synthesize a critical path of muxs, and the tool implements the mux using gates (Nand, OR ... etc). I am afraid this may increase the path delay while the std cell library contains mux cells. Is there a way to instruct the tool to use a std (...)
Hello all; i have assigned to design a 40 delay step using Nand NOR any standard cells currently I'm just looking at the big picture that i can start from. please any suggestions this 40 dealy step may take a 6-bit input to walk through the 40 steps of about 50 ps thank you in advance
Hi guys, Summary of Q's :D In cadence RC, upon clock gating, clock multiplexing or clock division, should I define the output clock from these modules in the synthesis script ? ---------------------- Detailed: I implemented a module with multiple clock inputs which I need to synthesize. say I have clk1_in &
I have made the following circuit where I have interface RFID and GSM with atmega16 using a mux. During simulation, I am getting "Logic contention detected " at T1out and T2out. I am unable to understand the error here. can someone explain the
I have written a VHDL code for a number of cascaded mux stages. During simulation it is observed that the syntax is succesfull and RTL schematic is generated. But I can't implement the test bench waveform. If any one know how to fix this please help me . It is urgent. I'm attaching the code with this. package body ---------------
Request, Can any one suggest me that how I can interface GSM and GPS both with 8051 microcontroller using Tx and Rx pin of them.. need circuit diagram or c code for them.. I want to send GPS data by GSM module as a message.. Please..:-(
Hi friends, I need to know the difference between the LUT and ROM. Please clarify the answer related to FPGA.
Hi All, I am using lpc2138 as i2c master to read eight ADCs(AD7400) using a mux(PCA9548a). After sending the slave address, i see only level high(NACK) in the SDA line instead of level 0(ACK). Attached the code and simulator screenshot(image location: ) for your reference.the control rema
Hi, I am trying to figure out what are the possible problems you could get if you connected a mux output to one of its inputs. So that when "select" is '0' it passes input1, otherwise it keeps the output value. I know that it's a combinatorial loop and EDA tools might complain, but how on earth could you get an unstable/oscillating situati