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11 Threads found on edaboard.com: Antarveena
Is there any one who has used Signal integrity in CADSTAR? As i am facing problem in doing simulation an error as follows @Simulation returned a fail with C:/ program / zuken Regard's antarveena
Hi All I have query that i need to set spacing rule of 3W for some clks signal ? how can i do it in Cadtstar 8 Regards antarveena
Press Ctrl +F in the find option go to >>> CODE >>> VIA CODE select the code you will find the respective one Regards antarveena
Hi all Can any body help me in generating .asc netlist from orcad and also tel me the procedure of importing it in pads Regards antarveena
hi Just Right Click on the schematic Page and go to Rename page and change the Page name Regards antarveena
Hello antarveena, I suggest you go through Hyperlynx Demos and Tutorials to understand the SI related simulations required. SI (Signal Inegrity analysis) 1) Cross talk 2) Transmission line terminations 3) Stack up calculations etc... PI (Power Integrity Analysis) This can also cause issues in your board. For PI refer the link for
hi FVM I want ans to be more precise can u plz tell me how to set spacing for particular net in cadstar regards antarveena How more precise than mattylad's reply do you want? What more information do you need? In schematic you assign a spacing class name to the net. in PCB you assign spacing
Can any body please help me out to find a good institute of Embedded system in delhi/NCR? regards antarveena
find your component here buddy and enjoy:D regards antarveena
Is it possible to get a report from Cadstar that lists the signal names of connections that go from one sheet to another in a multi sheet design? I cant see how, can anyone else? Thank you, antarveena
hi Raju For memory section you to make buses to be length matched and in the same routing layer clocks signal must be shielded if any and any differential should go parallel hope this will clear you regards antarveena