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7 Threads found on Array Signal Process
Xilinx and Altera both have the feature So, with Xilinx/Altera this code should always yield a "read_before_write" block RAM? type memory_matrix is array 0 to x of std_logic_vector(y downto 0); signal memory:memory_matrix; process(clock) is begin if rising_edge(clock) then memory (to_integer(address))<=in_data; end
hi, i am new to Vhdl. I have written a test bench which read real Data from a text file,store it in a array in vhdl testbench. Then i have converted it into Std_logich vector and store this new data in another array. I need to feed this array as Input to my testbench. I have done this with following code. type mem is (...)
What do you mean "display them circularly"? A circular buffer is pretty easy to implement, but I'm not sure what else you need. type dbuff is array (0 to 7) of std_logic_vector(7 downto 0); signal parmbuff:dbuff; | | | process(clk) begin if clk='1' and clk'event then parmbuff(1 to 7)<=parmbuff(0 to
Dear adityarajrulz, you can easily use a case statement, and put results directly into your target signal 'data'. Access to an array structure is done through integer index. Assuming you have access bits 'ai', you can do as follows: READ_process : process(address_i) is begin case address_i is when (...)
Hi, could anyone help me using the READLINE and READ procedures of the std.textio package? Say if I had a text file with numerical values seperated by whitespace, how could I intitialise an array with these values for simulation (Read them from the file one by one and into the array)? i.e. how can I use the READLINE and READ procedures to par
I have question regarding the interface to the TCD1304 toshiba linear array CCD. Where do I turn on the ADC? How is the integration time controlled? which signal clears out the reading? Anyone had experienece with this linear array? thanks ahgu
Don't quite understand what do you mean by display, if you wish to output an array at once, maybe you can try this: assuming you have an output pin: display_array : OUT std_logic_vector(your array size) then declare a signal: signal array_count : INTEGER (...)