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# Artificial Neural

699 Threads found on edaboard.com: Artificial Neural

## Neural network powered PCBa Visual inspection tool

We are developing a neural network capable of detecting faults on the electronics components placed on a PCB just from a photo taken of any PCBA. We are finally in the Alpha version of it: AgnosPCB.com Please feel free to take a look at our site and the current visual inspection tool: the web App[U

## Has anybody tried to run Keras or "Tensor flow" on FPGAs ?

Hello, as in title "Has anybody tried to run Keras or "Tensor flow" frameworks on FPGAs. I don't ask for runing trained ANN on FPGAs, but I rather asking about running neural networks in training phase. I hadn't eficient Nvidia GPU which is handle CUDA, so I cannot run KERAS on GPU, hence my question about running it on FPGAs. Maybe somebody

## In distributed amplifiers, is it total input capacitance of the gain stage or Cgs

In distributed amplifiers, is it the total input capacitance of the gain stage or just the Cgs of the input transistor that gets absorbed into the artificial transmission line?What do you mean by “the artificial transmission line” ?

## Design pi/2 artificial transmission line using lumped elements

Hi, I was reading the paper "Design Methodology for distributed Power Amplifier in Software -Defined Radio Applications" and came across "Once the characteristic impedances values are fixed, design can be completed by synthesizing the pi/2 transmission lines using lumped components and embedding the devices". I know how to make a tr

## Why the inductor equation is different in this paper

I saw the equation for inductance of the artificial lineThis is not transmission line. This is a cascaded connection of constant K section(L/2, C/2). As per equation 1 in the below figure, I think the Lb equation should not have /2 in equation (2). Coul

## Checkerboard shaped Artificial Magnetic Conductor array in HFSS or CST - Get RCS

So I have a checkerboard shaped array whose shape is of the form: 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 The surface of 1s and 0s sits atop a 1.4mm dielectric medium that is backed by a PEC, where the 1s represent very thin, square copper plates-- and the 0s-

## Skills from electronics/electrical engineers are more and more desirable?

Hello. I think this is a property forum.This is a thing, which I think about it more often. Viz, what skills from electronics/electrical engineers are more and more desirable? Well, my favorites thing about electronics are analog design, optics and and RF engineering, and I am doing it at big company since few years, and I like it. But are they a

## FPGA neural network training estimation time

Hello, Is there a formula to estimate how much time does a neural network need for training? I am trying to build a CNN for image processing, 640x480 images on Virtex 5 (without success however...). I have read articles about that, but I haven't seen anywhere talking about training time. Thank you...

## [moved] verilog code of a neural network

i have a trained neural network with 4 input neurons, 7 hidden neurons and 3 output neurons , 49 weights and 10 biases . Now i have to implement it on an FPGA . How do i start verilog code for this ?

## artificial Intelligence with plants

i am looking for a simple useful idea that use artificial inteligence and do at the same time something useful to plants. Can anybody help me with a good idea please ? When dealing with AI there is no standard approach, the nature of the dataset you have give you some indication of what could be done. The optimal solution comes r

## neuron modelling using MAC unit

I have finished designing a 16 bit MAC unit . now how should i implement a simple feed-forward neural network on FPGA using the MAC unit ?

## FPGA neural network training

Hello, I want to build a neural Network on a FPGA, and I will train it. What FPGA is capable for this work? I have a Xilinx Spartan 3E. Can I use this for this work? Can I build neural Network on this and train it? Is it better to use PYNQ solution, will it be more flexible? And a basic question I need help: If I manage to build a neural (...)

## Survey on FPGA-based Accelerators for Neural Networks

CNNs (convolutional neural networks) have been recently successfully applied for a wide range of cognitive challenges. Given high computational demands of CNNs, custom hardware accelerators are vital for boosting their performance. The high energy-efficiency, computing capabilities and reconfigurability of FPGA make it a promising platform for hard

## GSM Telit GL 865 Dual V2 acoustic echo cancellation with AT command?

1. One tactic you can try is to invert the waveform going to the speakerbox. Then it tends to cancel itself (instead of reinforce) as it comes again round trip through the mic and amplifier. The signal may already get inverted in your circuitry since it goes through a few amplfiers already. You may need to experiment to see what works best. 2. Sup

## Neural network implementation using VLSI

Hello forums, I am a beginner in the field of Analog neural Networks and thus seeking some guidance regarding it: There are a lot of research journals/thesis available online for the same, however, i couldn't find any single document/book summarizing all the different aspects, so if you can point me towards any reference from where i

## Neural network implementation using VLSI

Hello forums, I am a beginner in the field of Analog neural Networks and thus seeking some guidance regarding it: There are a lot of research journals/thesis available online for the same, however, i couldn't find any single document/book summarizing all the different aspects, so if you can point me towards any reference from where i

## OpenCL host code in Vivado

Hi all, I am actually working on neural network implementation on Zynq FPGA and I am going with Vivado HLS using OpenCL. I am totally new to OpenCL and a bit confused with how to write host code for the OpenCL kernel. Can anyone help me with this or suggest any resources? Thanks in advance

## Intern, Physical Design Engineer [July 2018]

Ampere is designing the future of hyperscale cloud computing with its 64-bit Arm server processor architecture. Born in and built for the cloud with a modern architecture, Ampere gives customers the freedom to accelerate the delivery of the most memory-intensive applications such as artificial intelligence, big data, machine learning and dat

## RC damping for second order filter

Filters designed according to a filter prototype (e.g. Butterworth, x-dB ripple Chebyshev) have a well defined Q set by the ratio of LC impedance to real source and load impedance. The problem with power electronics filters is that they have often low real impedance termination and varying load and source impedances. In this case, artificial dampin

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