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227 Threads found on edaboard.com: Artificial
Hello, as in title "Has anybody tried to run Keras or "Tensor flow" frameworks on FPGAs. I don't ask for runing trained ANN on FPGAs, but I rather asking about running neural networks in training phase. I hadn't eficient Nvidia GPU which is handle CUDA, so I cannot run KERAS on GPU, hence my question about running it on FPGAs. Maybe somebody
In distributed amplifiers, is it the total input capacitance of the gain stage or just the Cgs of the input transistor that gets absorbed into the artificial transmission line?What do you mean by “the artificial transmission line” ?
Hi, I was reading the paper "Design Methodology for distributed Power Amplifier in Software -Defined Radio Applications" and came across "Once the characteristic impedances values are fixed, design can be completed by synthesizing the pi/2 transmission lines using lumped components and embedding the devices". I know how to make a tr
I saw the equation for inductance of the artificial lineThis is not transmission line. This is a cascaded connection of constant K section(L/2, C/2). As per equation 1 in the below figure, I think the Lb equation should not have /2 in equation (2). Coul
So I have a checkerboard shaped array whose shape is of the form: 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 The surface of 1s and 0s sits atop a 1.4mm dielectric medium that is backed by a PEC, where the 1s represent very thin, square copper plates-- and the 0s-
i am looking for a simple useful idea that use artificial inteligence and do at the same time something useful to plants. Can anybody help me with a good idea please ? When dealing with AI there is no standard approach, the nature of the dataset you have give you some indication of what could be done. The optimal solution comes r
1. One tactic you can try is to invert the waveform going to the speakerbox. Then it tends to cancel itself (instead of reinforce) as it comes again round trip through the mic and amplifier. The signal may already get inverted in your circuitry since it goes through a few amplfiers already. You may need to experiment to see what works best. 2. Sup
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Filters designed according to a filter prototype (e.g. Butterworth, x-dB ripple Chebyshev) have a well defined Q set by the ratio of LC impedance to real source and load impedance. The problem with power electronics filters is that they have often low real impedance termination and varying load and source impedances. In this case, artificial dampin
"F" is a current-controlled current source (CCCS) - an artificial source of current.
This is an artificial Verilog-ism. VHDL is totally fine with this -- other than lacking +:. For Verilog, you can do: pass = &((status >> (i*N)) & ((1<<(N+1))-1)); // or pass = &((status >> (i*N)) & (N){1'b1}); although it feels like a hack. I'd like to know if there are better solutions. I think the last time I
Yes - you can. The most simple and exact method is to replace the s/C blocks with time-continuous (artificial) elements which then allow usage of the well-known simulation packages. In this case, also the periodic shape of the transfer function is preserved. For this purpose, two different methods do exist * Storistor method * Coupled controlled
How do you propose to do "Direct Torque Control, fuzzy logic, artificial intelligence" without writing any code?
Hi, 16 bit ADC vs 12bit ADC with oversampling: you need to average (or sum) at least 16 pieces 12 bit values to get a 16 bit value. But the 16 bit ADC has a DNL of typically +/-0.4LSB this equals to 0.025LSB at a 12 bit value. You won´t achieve the same with the 12 bit ADC.. You need to know: The "averaging" method only works good when the bit
Don't understand what the problem is. You can run the power supply with the actual GSM module, or connect an artificial load with a current waveform according to the GSM module datasheet. In any case, you would acquire the real current and voltage waveforms with an oscilloscope.
What seems an issue to me is a warning about "pcapacitor" being in the netlist but not in the layout. "pcapacitor" and "presistor" elements are supposed to be eliminated during netlisting step - but this should be configured properly in your environment. These elements are added to schematic to account for parasitic elements (and for net naming pur
A usual (and probably more appropriate) clock distribution scheme would connect multiple LVCMOS buffers to the oscillator output if separate buffered outputs are required. Don't know what the intended load of the clock distribution network is, but the shown design won't be able to achieve LVCMOS or TTL level. Regarding point 1, LVCMOS isn't
142024 Hello all Today I wanted to show a project that was created some time ago, As I did not have when to present it I decided to do it today. The controller for growing plants in the hydroponic system was created for hobbyist purposes, it may not be a professional controller, but it is enough for me. Maybe now a bri
Hello all. Today I wanted to show a project that was created some time ago, As I did not have when to present it I decided to do it today. The controller for growing plants in the hydroponic system was created for hobbyist purposes, it may not be a professional controller, but it is enough for me. Maybe now a brief description of what hydropon
the connectivity check does not show problems because - read the warning message - the tool (most likely - extraction tool) placed artificial "connector" resistors to make net's R network connected. These connectors have very small resistance (like 1 mOhm), and connect arbitrary nodes of disconnected R groups. Since these nodes are arbitrary - you