Search Engine www.edaboard.com

Artisan

Add Question

82 Threads found on edaboard.com: Artisan
If you can assume identical foundry, implementation of rules decks (and following of, in layout) and artisan skill, then you can predict equality of outcome. But there are a lot of fingers in various pies, between foundry, tools vendor, CAD librarian and layout that could add discrepancies. Now, if you let the tools auto-place and just pack to ru
Here's a functional schematic (from artisan): 98198
Hi all, In artisan library in Cadence I found lots of inverters named INVX1, INVX2, INVX3, INVX4, ... Anybody knows the difference between them? It's urgent for me to know about it. Thanks
Hi friends, I have a problem using the components available in artisan library in Cadence, when I put one inverter (INVX1) in the schematic and try to perform a simulation, he following error appears by Spectre. Anybody could help me, please? ERROR: Netlister: unable to descend into any of the views defined in the view list: "spectre cmos_
While using the rom compiler from artisan, I need to generate the verilog model for the rom. It requires a ROM code file. For 256 words and 32 bits, I have created a rom code file (source.rcf) that looks like this - 01010101010101010101010101010101 (line 0) 10101010101010101010101010101010 (line 1) . . . . . 1010101010101010101010101010
I need to understand how the layout area size of a SRAM changes as the number of bits of the data change. In another word I want to know the percentage of the overhead and the memory cells in different sizes. I assume that I should buy a tool from a vendor like artisan but I unfortunately can't. Is there any free memory generator tool that gives
for layout ,all the cells are from artisan std cell lib . for schematic ,all the cells are from vrilogin using cadence when i run lvs by calibre it show errors as follows: Ensure that this CDF has same terminal name as specified in this cell view. Nets will be printed in default terminal order for this component "Netlister :
Hi I have a main question. I have a design which I want to insert RAM module in the top module. I generated RAMs with artisan but I don't know how can I insert them in top?
Find here a DFFR from tsmc's artisan StdLib: 61094
Hello, I generate a dual port sram using artisan, then converted to .db file, set search_path and link_library pointed to the sram, and instantiated in my verilog code. I am using synopsys design compiler. But I got large timing violation problems on the CLKA and CLKB port of the memory. When I looked using "timing analyzer" as shown in the
what is artisan model in CMOS SRAM
hi when i link the artisan dual sram to my design using synopsys design compiler and report_timing i found that the path to the output port QB inherit a delay of 999ns which certainly violates the setup time the question is why this massive delay!!!!!!!!!!!!!! :cry: note : i use artisan dual SRAM compiler tsmc90nm plzzzzzzzz i need a quick r
I tried to request the artisan memory compilers from arm.com, but my request was rejected for unspecified reason. They used to be free downloads, but apparently ever since artisan was purchased by arm, it's now more difficult to get it. Does anyone know what qualifications one needs to have to get an approval? Alternatively, if someone ha
What you compared are not equal. How about this: single-port SRAM VS 1-port RF dual-port SRAM VS 2-port RF These are the options you have from ARM if you download them. Someone earlier mentioned about the minimum size of SRAM. artisan can't make really really small SRAM but they can make 1-port RF.
How to get these memory compilers? one easy solution is to check ARM website. artisans(currently ARM) memory compilers can be download by their free library program. Since u need a memory to talk with ur processor, check artisan library, i think they have register file compiler which could be more suited to ur need than the normal RAM compiler Wh
Hi, all I need a ROM run at 250MHz, and generate with IBM 0.13 foundry lib(ARM/artisan), use this ROM compiler: 8RF_RVT_VIA_ROM but when I generate with 250MHz, I checked .lib file of corner ss_1p08v_125c, the rising_edge is about 4.7ns, so we got a large negative setup slack, My question is what the highest frequency of the ROM generated by
Hi all. Now I have a problem. That is, I am using artisan memory compiler to generate some memories. I have noticed that there is a pin named "EMA" which means Extra margin Adjustment. In my design, How should I set this pin? Thanks very much
hi i'm in an asic project . we use tsmc 090 standard cells. we generated rams using artisan ! we use synopsys design compiler (synthesis) first encounter(layout) calibre(lvs , drc etc) to perform post layout simulation on modelsim , and verilog to spice netlist translation using calibre v2lvs , we enter the verilog file generated by the
Hi everyone, Could someone kindly give me a detailed procedure on how TSMC/artisan 0.18μm cell library could be installed for Synopsys design compiler. Thanks in advance eivala
see if artisan ip is available for your process