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34 Threads found on edaboard.com: Assura And Rule
Hi All, I am using the IBM process BiCMOS8HP. I have the following error from assura LVS, from Cadence Virtuoso: rule No. 78 : ###### SEVEN levels of metal M1-M2-M3-M4-MQ-LY-AM ##### There is no mention in the documentation about rule No. 78. Any one who knows about this error? Best Regards, Aba
Hi all, Please can someone help me with assura to PVS conversion? So how can I convert drc, erc and lvs rule files from one tool to another? Thanks for your advices.
Hi, I added a new device to a TSMC extraction rule which actually copied and modified from other existed device. I found my layout and schematic can be correctly netlisted. My problem is the LVS report showed the device in layout can't be found in "Filtered" and "Reduced" statistics. Problem is fixed. Thanks!
Hi all, I am using TSMC 65nm and I want to do extraction Virtuoso Layout Editing. But I deal with a problem: When I use Verify/DRC menu a window opens which uses assura for verfication, but it needs "Switch Names". I try to choose it from "Set Switches" but this item does not open in my window and it's deactivated !! When I try to (...)
I don't know what DRC you use, but I've made use of the get_texted() function in Diva, back in the day, for personal "ignore" rules logic. I haven't had the "pleasure" of hacking assura decks or using other engines. The alternative, I suppose, is to create some hierarchy which superimposes adequate connected metal, and then remove the (...)
Usually foundry provided assura rule file too. Why not ask for it from foundry?
Dear all, A few months ago I started working with the TSMC 65nm (CRN65LP v1.7a) PDK provided by Europractice services. At present I'm testing the full design-flow (from the schematic level to the post-layout simulations) through some basic exercises. Does anyone know if the entire physical verification (DRC+LVS+RCX) is supported with Calibre
Please refer to this link: assura rules file debuging - Cadence Community
you can get older version of the rules from tsmc. you can contact tsmc and aks them, and you can ask cadence for help. Also you can have a look into documentation for assura if the commands which give you errors are still supported or are obsoleted.
I am using IC5141 and I have neither assura nor Calibre installed. I am going to download one of these tools. Given a Cadence version, is there any rule in order to choose assura or Calibre? If I choose assura, which are the steps to follow after installation? I know I should add some settings in my (...)
Our foundry advises provides rule decks for all three tools. As per their notes, Calibre is better at detecting width/space violations and assura is better for density checks. Nothing specific about Hercules.
Dear Friends, I am using assura DRC and LVS. However, assura can not be started. The error message in CIW is: ibmPdkRunassuraDRC() *Error* eval: undefined function - vuiDRCRun <<< Stack Trace >>> (... in ibmPdkRunassuraDRC ...) ibmPdkRunassuraDRC() ERROR The (...)
Use Dracula or assura
No diva rules, but assura rule set? Then you should have a divaEXT.rul file and should be able to extract. LVS isn't necessary. Make sure that the Extractor can find the divaEXT.rul file. Without this file it won't work.
Dear all, I'm inserting Dummy_Metal_FILL by means of the following two files: Dummy_Metal_assura_90nm.20a : assura encrypt rule deck Dummy_Metal_assura_90nm_20a.rsf : assura rsf file I generate DM.gds with assura and then from icfb File-->import-->Stream I import (...)
Friends, I'm using IBM cms9flp technology for circuit design. When I tried to do DRC on my layout using assura-->DRC, an error message popped up, saying "Failed to build VDB, can't submit DRC run". I'm pretty sure the design rule path and switch name were correctly set.......Does anyone know what the problem might be? Any advice would be (...)
I've had this with assura a few times, and I've used the right layers for the pins. What I tend to find is that, a ground plane (we use metal 4 for gnd, and a light sheild) or whatever is floating, i.e. not connected to the grounds of the transistors etc, is floating. Have a look through your layout and make sure all (...)
Hi, how can i declare cells as blackBox while running assura lvs. What is the diffrence between avparameter rule and avcompare rule. ie, in both the place i can see blackBox . Regards, Analayout.
Does anybody know how to implement a DRC rule file in assura? How should this file look like? Where can I find informations about that? ... Thanks
Hello, I don't know really assura tool but with Calibre from Mentor you need basically your layout (*.gds), your source netlist (*.sp) and in option a rule file. In the rule file your are some information like where are your file on your computer the name of your output file(extracted netlist, report file,...). Be (...)