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49 Threads found on edaboard.com: Assura Drc And Lvs
Hello everybody, does anyone have experience on working with assura on Centos 7? assura drc is working fine, however lvs fails due to syntax errors after opening the .csm and .cls files for comparison. I know that Centos 7 is not supported, but using a 20 year old OS even in a virtual machine to (...)
Hi, I am doing a layout of a simple common-centroid differential pair with multipliers and fingers using IBM 130nm cmrf8sf. drc runs fine. But i get malformed device error: *ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device. Any ideas on how to solve this? Thanks.
Hi , Both PVS and assura lvs is from Cadence!. But what is the difference between these tool?
Hello friends, I am using UMC 90nm technology in Cadence6.1. I am able to view the results of assura drc and assura lvs but when it comes to assura RCX, then in log file it shows the error as no technology directory can you please help me in this.
Hi all, Please can someone help me with assura to PVS conversion? So how can I convert drc, erc and lvs rule files from one tool to another? Thanks for your advices.
Hi everybody: I am using AMS H35 tech for HV-Processor M0 Chip. The P&R and drc have passed. Now I am using assura to do lvs and encounter some wired problems. Who has some ideals? thanks and regards Error: Device 'cds_thru(Generic)' on schematic is unbound to any layout device (...)
Hello, I would like to make virtual connection between two same nets while the name are different. I can find joint nets function in assura but not in PVS, is anybody know how to do this in PVS? Thank you
Hi msdarvishi, My TSMC kit does not support assura, only Calibre. drc is strightforward : "runset" is not compulsory. In the kit installation directory, you should have a "Calibre" directory, with "drc", "lvs" and "rcx" subdirectories. Just load Calibre/drc/calibre.drc rule (...)
Is it possible to use Cadence design kit (gpdk045) for Calibre drc, lvs and QRC? I can only find assura rules in gpdk045, so if possible, how? Were the answers from the Cadence forum not good enough?
Hello, I am with problems to run assura and drc and lvs verifications. The Design kit that is being used is the IBM8rf-DM 130n. Before to start the design some configurations to setup the DK were done ( ). To test assura and drc analysis I designed a (...)
Dear all, I wonder if the tsmc 65nm kits are compatible with assura drc. Compatibility with assura lvs and assura RCX seems ensured, but I cannot made drc work... In the assura directory of the kit, there is no drc.rul or similar one, (...)
Hello My circuit is a decoder. I have created the layout of the circuit. I am using assura ams H35. and i have already passed successfully from drc and lvs runs. The next step is to perform the parasitics' extraction and run post layout simulations. But when i perform the parasitic's (...)
I am using tsmc90nm. I use autofilling tool provided by tsmc to do filling. When I didn't merge the dummy metal created by that tool, my lvs was correct. But when I merged it, mimcaps and several pins were not correctly bonded. Any idea why? ( My lvs with the merged dummy metal used to be correct). and my (...)
Hi there, I am using umc130nm and I am having problems in running drc and lvs checks. First of all, I am not sure about the tool. I know that usually Calibre or assura are used. Notwithstanding, when I launch the layout editor from the schematic, the only option is "Layout XL". After I lay (...)
hi, I can not see the av_extrated view in assura 317. I am using cadence 514 for schematic and by using SDL I am generate the layout which passses from zero drc and lvs match. but when I was try to run RCX it is failed. and one av_extrated file is generate which is blank. Thanx
Hi dipanjan, there are a few people in this forum that struggled with assura lvs in UMC18 (apparently you have problems even in drc), I have tried some of the devices in Calibre and they work just fine so I think is an issue with assura; make sure you are stamping your connection using a (...)
Before open the drc gui, make sure you have load the assura_tech.lib to the Technology under assura's menu. A sample of the assura_tech.lib looks like: DEFINE umc90nm_drc ./RuleDecks/assura/drc DEFINE umc90nm_lvs (...)
Hi! i use Cadence and assura for the drc and lvs in Layout XL. I fill the form of assura lvs and choose the right technology files in each box and i choose the DFII option. BUT when i click ok an error message appears which says: "The (...)
Hi serhannn, Please when posting a drc/lvs/QRC error you should be more specific,that is you should show the exact error given by assura/calibre etc...For your case,i think that you should create a n-well contact ring around your pmos transistors and then connect this ring to Vdd.Give it a try and see if (...)
Dear Friends, I am using assura drc and lvs. However, assura can not be started. The error message in CIW is: ibmPdkRunassuradrc() *Error* eval: undefined function - vuidrcRun <<< Stack Trace >>> (... in (...)