Search Engine

Assura Drc Error

Add Question

48 Threads found on Assura Drc Error
which drc are you using, assura or calibre? does the error exist when you use the other one with "CHIP" design type? contact MOSIS if you are a customer MOSIS_Users_Group : MOSIS User's Group
Hey! I've designed an LNA in Cadence (TSMC 0.35um CMOS technology). After successfully running drc and LVS, when I tried to run RCX on my layout design, it gave the following errors: 'Can't access compare.rul' 'error loading master control file rcx.trial2.rsf' (my cell view name is trial 2) 'error in loadstring' I read over (...)
Hello, Today i came up with an error during drc analysis to my is also present when i run a design rules check only to the mimcap and not to all the design.The error is : GRQCAP7aJT : QT Maximum Area 100um^2 I checked the design rules,in the appropriate section of the design manual,for further information but it doesn't s
Check this error message string in your assura drc (or ERC) rules' file. The rule violation generating this error message should give you a hint. I'd suspect that your substrate taps are connected to different nodes, which is not allowed.
edit your assura load file and comment out ASSUME_KERNEL 2.4 or something like this. hock
hi all.. I am doing layout in cadence virtuoso tool. When i run assura drc(Design rule checking) to debug the errors its showing one error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um. Its indicating at every NMOS in the design. I am unable to clear this one. plz help me out .
To overcome this problem you need to do a small change in the drc rule file.First go to /RuleDecks/assura/drc, then open "G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-assura-drc-2.10-p1.rul" file -> go to the last line which is "load( (...)
I get the following error when I try to run drc check in the Virtuoso Layout Editor window in cadence IC6.1. *error* eval: undefined function - vuidrcRun <<< Stack Trace >>> (... in ibmPdkRunassuradrc ...) ibmPdkRunassuradrc() Does anyone know how (...)
There are two different Vdd in my schm. Avdd and Dvdd, but assura can't indentify still report the error that the Nwell is not connected to the Vdd. Declare these nodes as global (Avdd! & Dvdd!), then it should work. See also this topic .
u have to add the TECHNOLOGY file in assura TEchnology,after that in assura drc window ,u have to add this ./assuradrc.and add asuura technology file
Friends, I'm using IBM cms9flp technology for circuit design. When I tried to do drc on my layout using assura-->drc, an error message popped up, saying "Failed to build VDB, can't submit drc run". I'm pretty sure the design rule path and switch name were correctly set.......Does anyone know what the (...)
Hi, Dear Friends, assura drc shows some error like this: Ratio (RX TripleWell contact)/(NFET gate not over N3) >= 0.004. This is an error related to Latch up. There are already guard ring added to the active components. What are some other method which will eliminate latch up? Thanks a lot. Adam
Hi Friends, I got some error when doing drc using assura: Rule No. 815 : GRLUP09b: Ratio (RX substrate contact)/(NFET gate not over N3) >= 0.007. I am not sure what this message means. Would you please give me some hint? Thanks, Adam
Hello all. I have two lateral pnp transistors contained within one well. They are diode connected (i.e. the base and collectors are connected together). When I run assura drc I get the following error: 2 bad_n_well_welltap_multconn_erc and the two base contacts of the lat 2 transistors are highlighted. I understand that (...)
Hello all. When I run assura drc on my layout I'm told there is one "DataAuditerrors". The area highlighted in my layout that is the cause of this error is a ring substrate contact (I have this for no other purpose other than as a contact for electrochemical etching. i.e. it serves no purpose in any active or passive (...)
Hi, assura uses DFII format for running drc/LVS and DBU ---Database Units and mostly calibrated to microns. So all values/diemensions of devices should be in multiples of 1000u/0.1u or anything of that sort.The DBU details will be present in the ruledeck file. So if you refer to your ruledeck and check for the units then you can solve this (...)
For my layout, I have passed the drc and LVS checking using assura. As I do the extraction in RC or R only extraction mode, it gives out the error and stated: *error* FAILED ASSERTION at ?reconnect?: RCX net 1722 cannot be mapped to LVS net If I use C only extraction mode, it could do the extraction. Could (...)
After renew the license, I run the assura RCX with error. (drc and LVS are alright) But it is only happened in sparc Solaris machine, it is alright in x86 Linux machine. I use same layout to do the test. Both Linux and Solaris use IC5141 and assura3.1.7. Please help! RCX error message (...)
Probably you're not using a recent enough assura version. What is the technology that you are using? look the design kit compatibility.
I have IC5141 and assura 3.12 on my pc with CentOS 4.5. When I tried to drc with assura, I got the error message: "Failed to build VDB. Cannot submit drc Run". In the log file I saw "error: Illegal modifier: "withIntersection" Please, help me Thanks