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What is the difference between the Sampling Bandwidth vs. Bandwidth in Tracking Mode of a Sample/Track and Hold Amplifier ? Is Bandwidth in tracking mode different then the sampling bandwidth ?
Hello. How to highlight all differences in the layout as "flattened" and not as "hierarchical"? I'm using Calibre XOR + rve.
Hello, hope everything goes well, and covid19 will stop soon.. I am very new in Verilog, use xilinx vivado 19., want to add ddr3. what a problem cannot understand.. clock wizard and mem modules done normally step by step as in instruction..code i got from https://nu
Hi everyone, I am using Altium 18. I want to put two components with a same footprint on top of each other. I was able to do that in Altium 16 and before, but I am not able to do that. I disabled all the rules, but still, I cannot do that. I would be grateful if you give me a hint. Thank you
Hi all, I have simulated a comparator. Before the comparator trips where it should it trips a bit earlier with no apparent reason. I am using gear2only and tried traponly and when using the trapownly I don't see this strange behaviour. Basically I am sweeping the input of the comparator very slowly against a reference to assess the offset. Is t
Greetings ... comment that I am with a small project in ISE 14.5, I have managed to synthesize but I am having compatibility problems with the ipcore fifo_generator 9.3 when implementing and I am having one of the errors. error:NgdBuild:604 - logical block 'u_client.U_client_ff' with type 'g1_ipcat_wbus_client_fifo' could not be r
I'm having an error about adding 1 to a std_logic_vector in VHDl. Here's the code: It's a 74LS163 Synchronous Binary Counter code. LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; entity AAC2M2P1 is port ( CP: in std_logic; -- clock SR: in std_logic; -- Active low, synchronous r
f398 spice This is from Orcad: ************************ .subckt LF398H 3 8 7 4 6 5 1 2 pin 2 behaviour is not defined, error(ORPSIM-15108): Subcircuit LF398H used by X_U8 is undefined please resolve this issue Thanks & Best Regards, Vijendra Jois
I am modeling LDO in PSpice, here i have selected spec as ZXCL280 in dropout vs output current I have understood this as resistance of the MOSFET from dropout graph. That is minimum resistance required for the MOSFET, 2 OHMS (Page No 4). I will be using Ron=1/kp(Vgs-vt)
I have tried building clock tree in icc2.but tool is not able to achieve target latency and skew, also I have one 1 drc(trans) violation so drc could not be the reason. From where I should start my debug for this behaviour of tool.
I have tried building clock tree in Icc2. But skew and latency of clock tree which is generated is not matching with target skew and latency. I am not getting the reason why tool has not achieved the target value for skew and latency. I have only 1 drc violation, still tool not able to perform task nicely.
Hi, I'm working on an example that is provided on Proteus simulation examples. I opened a file that contains a circuit that has 2 AC sources, which I don't know why they used 2 AC sources, so I deleted one and started to get the results I want. But another problem that I got is that if I add a ground to the circuit, then a fatal simulation
Hello, Is it possible to have two sets of PBC offsetted as shown in the attached? I ran it and gave no error, the question is if it is correct. Thank you
Hello everyone, I'm having trouble solving this problem with two software . A simulation error occurs when I try to simulate. 158172 Follows the image and model (code)158173 Source:
Hello everyone, I want to use SMS7630-061 in my design in ADS. The packaging of it is 0201, I want to draw it in ADS. However, after I 'create EM model and symbol' and 'generate layout' in the schematic, the Pin in the layout of the symbol changed its position. The picture is attached blew. What should I do about it? Can any of you help? T
I've no previous experience with 8051 MCUs. Recently I was trying to work with AT89S51 MCU. I'm having Chip Enable Program error when trying to upload hex to MCU using Progisp1.72 158127 I checked many times to ensure this wiring to connect with MCU: 158128 Tried two different usbasp progr
Hi, I'm trying to understand RDSon a little in this circuit and a difference amplifier output voltage. I suspect that such low RDSon is either my bad maths or a very idealized PMOS model as it doesn't seem to look realistic when I try to understand the datasheet curves and relate them to my VGS and load current. I think 86mV out of diff am
Hi, Suppose I have an incorrect nets error at the cell level in lvs. For eg: if I have a cell and2x2, and the tool is reporting "incorrect nets" error under this cell, besides the top level cell. My question is, since there are many occurrences of the above cell in the layout and source, on what basis is this "incorrect nets" error (...)
Hi all, I am fairly new to HFSS, and unlike python or MATLAB, the resources are few. I am trying to create a linear array such that I can simulate the beam pattern, get the array factor and also see the effect on the beampattern with and without mutual coupling. I havetrie the unit cell array method but I keep getting error when setting up the r
Hi dear friends. I came across this concept and I would like to appeal to the skillful people with experience in real world design what DFM rules are, advantages and disadvantages and how they differ from custom set of rules? Came across this concept recently and I have never heard about it. Searching around the web I can't find a lucid explanatio