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48 Threads found on Assura Drc Error
HI I have a problem with virtuoso and AMS 0.35 I insert a pmos but I always receive the same error and I do not know how to fix it I puts a pmos for the library 136066 De assura drc indicates BAD_SUBSTR_SUBTAP_FLOAT_ERC but I think the substrate is well fed to VDD thanks.
minimum top via enclosed by metal top 1 is 0.01micron... How to fix this error.. I am using 8Metal layer process? It appears when i place metal 6 and Top metal via top.
Hi there, I'm making an OTA layout in Cadence, ams 0.18um (cmhv7sf). The only drc error I have is about I/O wirebond - it says that some transistors don't have body contact while there are n-well contacts. When there where contacts on the left and right side errors where the same. 133931133932
I guess I'd begin with, is assura the selected drc engine? If {whatever} doesn't like the drc deck that's purportedly for assura, you have to wonder who you're talking to. And then I'd be looking to gpdk message boards for any stuff about drc setup particulars for the 45nm kit.
Hi, I am doing a layout of a simple common-centroid differential pair with multipliers and fingers using IBM 130nm cmrf8sf. drc runs fine. But i get malformed device error: *error* Device 'nfet(Generic)' on Schematic is unbound to any Layout device. Any ideas on how to solve this? Thanks.
Hi everybody: I am using AMS H35 tech for HV-Processor M0 Chip. The P&R and drc have passed. Now I am using assura to do LVS and encounter some wired problems. Who has some ideals? thanks and regards error: Device 'cds_thru(Generic)' on schematic is unbound to any layout device Device 'RDIFFP3(RES)' on Layout is unbound to any (...)
Hello everybody: When I finished P&R Layout in encounter, I use assura to do drc. However I find the following violations. Do you know how to figure out them ? Do I need to do some special configurations in Encounter? I am using the AMS-H35B4-ThickallMeta tech. Best Regards INFO : standard pad met4 4 stack rvia2 INFO : rvia2 does
105140 I am trying to verify above drc error (Enclosure rule). This is what is there in the assura rule file. L48775=geomStraddle(Nwell Nburied) L92003=geomAndNot(L48775 Nburied) errorLayer(L92003 "NBL.E.1: Minimum Nburied to Nwell enclosure >= 0.2 um") L91383=drc(Nburied Nwell enc<0.2) (...)
Hello, I keep getting the above error when attempting to run assura drc on a simple layout of an inverter. I am using IBM 90nm technology. Additionally, here are some of the errors in the Cadence terminal: *No tech lib map file 'assura_tech.lib' or 'pvtech.lib' found. *No rule sets can be created because (...)
Hello, I Keep getting the "Failed to build VDB. Cannot submit drc run" error when I am trying to run assura drc in my layout. In the cadence log, it shows that many layers are undefined as well. We are pretty sure it's because we are using assura version -614 and layout version -615. Is there anyway to get (...)
hii , I am new to layout . I use assure for drc checks , and I have an error : "PP.EN.2 3 enclosure of PW strap >=0.03 " I only used OD (oxide diffusion ) on the layout editor , and th error came by . Plz help me in resolving this , thnx
Hello My circuit is a decoder. I have created the layout of the circuit. I am using assura ams H35. And i have already passed successfully from drc and LVS runs. The next step is to perform the parasitics' extraction and run post layout simulations. But when i perform the parasitic's extraction, I get this error (...)
Hi all, I want to perform post layout simulation of sram cell in cadence 6.1.4. I have completed drc n lvs steps successfully with assura.But i can't extract gives error that "no directory found". I have attached screenshots of settings for directory please help me if anybody can solve this problem...Thanks in advance...[A
Hi everyone, I am using AMS 0.35um process.I am getting BAD_SUBSTR_SUBTAP_FLOAT_ERC error while running assura.Please someone help me in debugging this error and how to solve this. Thanks
Use the search facility here in the forum,you will find various reports for this problem from the past and maybe some solution. Also : 1.)Make sure that you have the correct metal stack attached to your library. 2.)You have the correct paths in you shell file (.cshrc file for example) for the assura tool and that you use the correct version for y
I am using tsmc90nm. I use autofilling tool provided by tsmc to do filling. When I didn't merge the dummy metal created by that tool, my lvs was correct. But when I merged it, mimcaps and several pins were not correctly bonded. Any idea why? ( My lvs with the merged dummy metal used to be correct). And my drc is clearn.
Hi! i use Cadence and assura for the drc and LVS in Layout XL. I fill the form of assura LVS and choose the right technology files in each box and i choose the DFII option. BUT when i click ok an error message appears which says: "The specified SKILL device information file was not found". The technology files are (...)
Hi, all, could you help me? assuraoa3.1.7, ic6.1.3, MMISM07 were used. when assura drc run for the firstly several times, they were successful. But afterwards it always said failed, and in the log file it wrote "error unknown: unable to create library "assuraOutLib"". What's wrong with (...)
Go to assura Tab (upper menu of Virtuoso L/XL Layout Editor) and choose "Open ELW".Then select all errors and press the NV button above.This will delete all highlights from your screen. Regards, Jimito13
Hi serhannn, Please when posting a drc/LVS/QRC error you should be more specific,that is you should show the exact error given by assura/calibre etc...For your case,i think that you should create a n-well contact ring around your pmos transistors and then connect this ring to Vdd.Give it a try and see if this corrects the (...)