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Assura Drc Errors

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15 Threads found on edaboard.com: Assura Drc Errors
Hello everybody, does anyone have experience on working with assura on Centos 7? assura drc is working fine, however LVS fails due to syntax errors after opening the .csm and .cls files for comparison. I know that Centos 7 is not supported, but using a 20 year old OS even in a virtual machine to support those tools (...)
Hi there, I'm making an OTA layout in Cadence, ams 0.18um (cmhv7sf). The only drc error I have is about I/O wirebond - it says that some transistors don't have body contact while there are n-well contacts. When there where contacts on the left and right side errors where the same. 133931133932
Hello, I keep getting the above error when attempting to run assura drc on a simple layout of an inverter. I am using IBM 90nm technology. Additionally, here are some of the errors in the Cadence terminal: *No tech lib map file 'assura_tech.lib' or 'pvtech.lib' found. *No rule sets can be created because there are no (...)
Hi, Iam doing a layout on Low Noise Ampifier in 0.13um technology using assura Layout XL. I have encountered with drc errors such as 1. Minimum DIFFUSION Density over 500x500 um^2 is 20% 2. Minimum PO1 density over 1000x1000 um^2 is 15%. Can anyone please give me a solution to solve these errors. And also, I want (...)
you can get older version of the rules from tsmc. you can contact tsmc and aks them, and you can ask cadence for help. Also you can have a look into documentation for assura if the commands which give you errors are still supported or are obsoleted.
Hi, I am doing layout in ibm cms9flp. When running assura drc, then I got errors like: GR999a:All PC polygons must be within CHIPEDGE GR999a:All M1 polygons must be within CHIPEDGE GR999a:All (CA or CA_bar) polygons must be within CHIPEDGE etc. Could anyone please suggest me what can I do to satisfy this rule? Thank you,
Hey! I've designed an LNA in Cadence (TSMC 0.35um CMOS technology). After successfully running drc and LVS, when I tried to run RCX on my layout design, it gave the following errors: 'Can't access compare.rul' 'error loading master control file rcx.trial2.rsf' (my cell view name is trial 2) 'error in loadstring' I read over some forums that you nee
i am facing a trouble in assura. I did all flow in encounter for a digital project. Then, when I import the def in Virtuoso and play the drc with assura I have several erros because the via isn't coincide with pins of the standard cells. I try something in encounter but doesn't work. Somebody can help me?? Thanksss
Hi All, I am able to run assura drc without any errors but it is not listing all the errors. It is just listing density errors. but when i checked in rules file all the rules are there in rule file. can anyone say what might be the problem? Regards, Sree
I take it from the errors that you're using an IBM PDK? Insert Image_bevel, set the dimensions of your chip and make the origin (0,0). If you're not in the final stages of your design, you can do Calibre and assura drc with the "Cell" switch on so that it doesn't do checks related to CHIPEDGE.
hi all.. I am doing layout in cadence virtuoso tool. When i run assura drc(Design rule checking) to debug the errors its showing one error like"MAXIMUM n+ DIFFUSION TO NEAREST p+ PICKUP SPACING(INSIDE P-WELL OR TWELL) IS 20um. Its indicating at every NMOS in the design. I am unable to clear this one. plz help me out .
I have used assura and CALIBRE and both are quite good for drc, LVS and RCX. Although I found CALIBRE to be quite painful when it comes to representation of some forms of LVS errors. Both these tools are widely used in industry and supported by almost all foundries.
Dear fellow designers, I have a question concerning some errors setting up my drc/RCX runs in virtuoso Layout XL: The Run assura drc window keeps saying "Failed to build VDB. Cannot setup drc" When I check my Log, I see the following errors: *Error* load: can't acces file - (...)
you can load (start) Calibre inside Virtuoso However, Calibre rule is not 100% compatible with either Dracula rule or assura rule
Hi I am working on Cadence - Virtuoso Platform. I have assura as an Stand Alone Application . I want to invoke assura into the Cadence DFII Frame work so that I can perform drc,LVS. Kindly help me in this issue . I have been trying to invoke the assura into the Cadence DFII Frame work but I am encountering the (...)