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129 Threads found on Assura Drc
Hello everybody, does anyone have experience on working with assura on Centos 7? assura drc is working fine, however LVS fails due to syntax errors after opening the .csm and .cls files for comparison. I know that Centos 7 is not supported, but using a 20 year old OS even in a virtual machine to support those tools has countless (...)
HI I have a problem with virtuoso and AMS 0.35 I insert a pmos but I always receive the same error and I do not know how to fix it I puts a pmos for the library 136066 De assura drc indicates BAD_SUBSTR_SUBTAP_FLOAT_ERC but I think the substrate is well fed to VDD thanks.
Hi, I am trying to run drc but in technology it's not showing my library i.e. cmos150 nm. even I have attached in startup of schematic and schematic is runing fine but for layout drc is not running. Please give anyway to resolve this issue. Thanks
minimum top via enclosed by metal top 1 is 0.01micron... How to fix this error.. I am using 8Metal layer process? It appears when i place metal 6 and Top metal via top.
Hi there, I'm making an OTA layout in Cadence, ams 0.18um (cmhv7sf). The only drc error I have is about I/O wirebond - it says that some transistors don't have body contact while there are n-well contacts. When there where contacts on the left and right side errors where the same. 133931133932
I guess I'd begin with, is assura the selected drc engine? If {whatever} doesn't like the drc deck that's purportedly for assura, you have to wonder who you're talking to. And then I'd be looking to gpdk message boards for any stuff about drc setup particulars for the 45nm kit.
Where can I find assura drc rule deck file in our project path. "drcExtractRules" I guess this would be the name of the file. Thanks in Advance. Best Regrds, Lakshman
Use foundry provided Density rules - as freebird stated above.. these are kind of drc rules.. Calibre, PVS, assura can do a density check. Back to Basics: Metal Density - is a point function, and therefore various functional representations are possible, {there is nothing like absolute value of density}. That means - different functional represent
Hi, I am doing a layout of a simple common-centroid differential pair with multipliers and fingers using IBM 130nm cmrf8sf. drc runs fine. But i get malformed device error: *ERROR* Device 'nfet(Generic)' on Schematic is unbound to any Layout device. Any ideas on how to solve this? Thanks.
Hi all, Now I am researching how to check floating gate on assura. Pls help me how to check it. Thanks, Sky
Prashanth, Cadence PVS (Physical Verification tool) is an advanced drc/LVS engine for drc and LVS check. PVS is specifically for technology nodes below 45nm. Cadence assura is an older LVS engine which can be used for technology nodes above 45nm.. i.e, 180nm, 130nm.etc., Summary : PVS for 45nm and smaller Geometry (...)
Hello friends, I am using UMC 90nm technology in Cadence6.1. I am able to view the results of assura drc and assura LVS but when it comes to assura RCX, then in log file it shows the error as no technology directory can you please help me in this.
Hi all, Please can someone help me with assura to PVS conversion? So how can I convert drc, erc and lvs rule files from one tool to another? Thanks for your advices.
Hi everybody: I am using AMS H35 tech for HV-Processor M0 Chip. The P&R and drc have passed. Now I am using assura to do LVS and encounter some wired problems. Who has some ideals? thanks and regards Error: Device 'cds_thru(Generic)' on schematic is unbound to any layout device Device 'RDIFFP3(RES)' on Layout is unbound to any Schematic de
you could read the drc report from assura in Encounter and fix them by hand. but first, the design from Encounter is drc clean? if yes, you must understand why these error are not seen by encounter.
105140 I am trying to verify above drc error (Enclosure rule). This is what is there in the assura rule file. L48775=geomStraddle(Nwell Nburied) L92003=geomAndNot(L48775 Nburied) errorLayer(L92003 "NBL.E.1: Minimum Nburied to Nwell enclosure >= 0.2 um") L91383=drc(Nburied Nwell enc<0.2) errorLayer(L91383 "NBL.
Hello, I would like to make virtual connection between two same nets while the name are different. I can find joint nets function in assura but not in PVS, is anybody know how to do this in PVS? Thank you
Hi msdarvishi, My TSMC kit does not support assura, only Calibre. drc is strightforward : "runset" is not compulsory. In the kit installation directory, you should have a "Calibre" directory, with "drc", "lvs" and "rcx" subdirectories. Just load Calibre/drc/calibre.drc rule file for default (...)
Hello, I keep getting the above error when attempting to run assura drc on a simple layout of an inverter. I am using IBM 90nm technology. Additionally, here are some of the errors in the Cadence terminal: *No tech lib map file 'assura_tech.lib' or 'pvtech.lib' found. *No rule sets can be created because there are no defined (...)
Hello, I Keep getting the "Failed to build VDB. Cannot submit drc run" error when I am trying to run assura drc in my layout. In the cadence log, it shows that many layers are undefined as well. We are pretty sure it's because we are using assura version -614 and layout version -615. Is there anyway to get around this (...)