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In QRC in there are two options for generating SPEF, one is Transistor SPEF, and the other is Cell-level SPEF. You need "Cell level SPEF". Standard approach in assura LVS - is to supply all stdcells/macros in ?dspfcells or ?preserveCell. The following restrictions should be kept in mind when specifying the DSPF cells:  * All DSPF cells must have
Hi I am having issues with PVS or assura LVS checking the finger numbers of mosfets in the layout vs. schematic. The LVS tool seems to ignore this parameter mismatches. Is there anyway to enable this function? Thanks,
Error obtain in LVS is 1)Rewires 2)nets 3)device I m sending the screenshot of LVS with error window. Please give us solution for that error.
Hello I in the following attached photo I am trying to find where is assura tool , I only can find the Verify Menu in virtuoso. My question is Where is assura menu like this one in this tutorial ? and what is the tool that virtuoso using if I used this verify menu ?!!! Th
If your particular PDK allows permuteSD (or whatever the LVS tool of choice likes to call it) and this is a simple symmetric MOS (not extended-drain, LDMOS, etc.) then there's no LVS difference and you don't have to set anything. I found, though, in one assura setup that this aspect needed messing-with and was not very obvious. I forget the detail
Hello, Is seems like your extraction tool use real capacitor and resistors instead of pcapacitor and presistor. But I don't shure with it. Do you have other extraction tools? assura or calibre maybe...
Prashanth, Cadence PVS (Physical Verification tool) is an advanced DRC/LVS engine for DRC and LVS check. PVS is specifically for technology nodes below 45nm. Cadence assura is an older LVS engine which can be used for technology nodes above 45nm.. i.e, 180nm, 130nm.etc., Summary : PVS for 45nm and smaller Geometry assura (...)
Hi all, Please can someone help me with assura to PVS conversion? So how can I convert drc, erc and lvs rule files from one tool to another? Thanks for your advices.
Hi all, Can me someone explain different (advantages, disadvantages, using) between assura,QRC,RCX,PVS tools, because i dont understand the using of these tools from datasheets very well. thank you very much
When I start assura independently by using command "avv", there is error message "ERROR: oaGetLibPath cannot be executed because the /usr/cadence/IC615/share/oa/bin/linux_rhel30_gcc44x_32/opt", anyone had this problem before, please help me. Thanks very much in advance.
Hi all, I want to check the floating metal and floating gate on my layout, and I use assura tool. I red assura Physical Verification Command Reference, it wrote ercFloatingNets and ercFloatingDevices can solve floating metal and floating gate promble. I use xfab_018. Please help me, if you know how to do with this. Spring
I used the lvsIgnore = true statement on an analogLib resistor in the schematic. This is working fine. But I do not know, how I should proceed in the layout. There are now 2 pins on one net - that is P_GND and GND, which is correct. I read a bit the assura manual.. and there is an option to join two nets - but I did not find an option to jo
hi....... tools like calibre,hercules,assura using these we can check the depends upon the vendor 's rule deck file..They will mention the tool to be used for certain rule file.. Thanks ,we have herculus in our college computers.
You can get the netlist file of your layout only if there is a schematic corresponding to your layout. That's not quite correct, I think: The extraction tool (diva, assura, calibre) can extract a netlist from a layout -- it doesn't need a corresponding schematic for this. Only the LVS tool needs it.
Greetings everyone, Since I couldn't find a similar topic I decided to post my problem : I am using Faraday Mem Maker along with UMC90 technology for SRAM generation. In general, I want to use the .gds and .siz (net list) files from the me maker tool to perform some post-layout simulations with Hspice. The flow utilises cadence 5 and assura 4.1
Well, the correct answer is Caliber, because, the right name is Calibre :) . To be serious, it depeneds on used technology: for nanometer techs, the widely used tool is Mentor Calibre. Synopsys Hercules is still used, but it is enough old and replaced by Synopsys IC Validator. Regarding assura - it may be used for old technologies only, for exampl
What do you mean with ...But it doesnot include any parasitic.?When QRC (i suspect you use assura tool for extraction,right?) finishes and you are back-annotating the parasitics on your schematic what do you see? Also provide your QRC tabs' setup,maybe there is something wrong.
assura is junk tool and has its mood . you could do one thing remove assura working dir in your design, remove all hidden files .assura in your login account, and try to run assura ( cadence calls it cleanup , !) may be helps
Need more clarity on the question. RFMOS "device" extraction should be happening at the LVS extraction stage - what does that has any relation with RCX? If this is LVS problem - which LVS tool Which technology? layout of "big" and "small" rfmos may help, overall more details will help.
Use the search facility here in the forum,you will find various reports for this problem from the past and maybe some solution. Also : 1.)Make sure that you have the correct metal stack attached to your library. 2.)You have the correct paths in you shell file (.cshrc file for example) for the assura tool and that you use the correct version for y