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70 Threads found on edaboard.com: Asynchronous Counter
I am wondering how to draw a state transition diagram for a two bit counter with the same reset capabilities of a register. I am also wondering if this reset signal is asynchronous what does this change about the output function and is it a Mealy Machine?
Why would you design an asynchronous counter in an FPGA!? That is not recommended under any circumstance.
Hi I am trying to design a Mod 6 3-Bit D-type asynchronous down counter using Pspice and I am having difficulty with the Nand gate in order to make the count go from 5-0. In its present state it is counting from 7-0 and I know with the addition of adding a NAND gate I can reduce the count to the desire 5-0 but I have no idea how to connect the g
There are special design methodologies for sequential asynchronous circuits. Following these methods, it can be possible. You only mentioned a bare idea instead of giving a logic circuit. Thus we can't see how your design fails.
Hi everybody, today I have a problem conected with design asynchronous counter mod 12 D. I use OR4 to detect for a while state "1111", because I want to reset counter to state "1101", but it's not working... On symulation we can see that counter reset his state after detected state "0111", before was state"1000", so (...)
I wrote a frequency counter program in PICBASC PRO for 16F88. This is a pretty standard stuff: timer1 is an asynchronous counter and timer0 is a clock. When I run this counter in Proteus, everything is OK if I feed B6 timer1 pin with the digital clock signal (it works up to 100 MHZ). But when the signal is not digital (...)
This is somewhat similar to what I wrote in #3 - the difference is that I use an asynchronous reset from the receiving clock domain to clear the DFF. Back to my question: Do you see any benefits in using the solution proposed in this link:
problem 1 you can't create asynchronous counters if you want something that will actually work on hardware. Verilog isn't like C programming it's a hardware description language and the bellow code does not describe a counter. always @(start) begin if (clk_divider == 4'b1000) begin // divided by 8 sck = ~sck; end if (clk
4GHz binary counters are all asynchronous like this can get synchronous counters up to 1.4 GHz with async reset, but very
The schematic in post #4 gives a first clue what you actually want to achieve. We see a mux circuit, apparently intended to scan the four digits one-by-one. Presently this part doesn't work. The 74163 clear input is an asynchronous one, thus the counter is immediately reset when counting from 2 to 3. The fourth segment won't be lighted. Plea
hi, Look at this image, it suggests a external asynchronous 1imer clock period of 60nanosec, ~16MHz. Use timer0 in conjunction with a timer0 interrupt clocked software counter to give a precise 1 second period for reading the Timer1 count. Also use timer1 interrupt to clock a software counter, this will give a 24 bit value [ 8bit in (...)
The bad asynchronous circuit must be expected to bring up all kinds of unpredicted behaviour. Also simulation results are likely different from real circuit behaviour.
I'm working on an asynchronous problem! so I can't work with this solution! :/
Write 5 applications using Timer1 1. asynchronous Clock Mode (read AN580) 2. counter 3. Control the operation of electrical devices based on a programmed schedule (Simplest application is LED Blinking) 4. Delay (Timer Based) 5. Digital Clock Write 5 applications using Timer 2 1. Color Sensor (using TCS230) 2. Delay (Timer Based) 3. Sonar Range fi
IC-74196 i.e. 4-bit asynchronous decade counter with /2 and /5 sections, load and reset..
Hi i want a verilog hdl code for a 4 bit asynchronous counter using reversible logic gates.
Definitely not the right way. The counter can't work at all in a level triggered (asynchronous) always block. Think about a synchronous design based on the clock input. After synchronizing the button input in a register chain, count it#s high and low states, etc.
In the sn74als161b datasheet there is nothing written about spikes - does this mean that unwanted spikes can't happen on the last stage of a cascaded counter (sn74als161b)? RCO isn't intended for asynchronous use. Spikes have to be always expected for combinational signals. RCO can be used as a synchronous signal or needs to be regi
An up/down counter with Up/Down clock inputs is like the 74HCT193. But with two asynchronous clocks for up and down it is needed to synchronize them to avoid metastable conditions. Thus you have to synchronize both with a higher clockfrequency to avoid to get a up and down clock at the same time. Maybe this website will help in the design:
Config each DFF as a divide by 2 - i.e. connect Q/ to D and input clock to CLK. Now connect them in series - Q1 - CLK2, Q2-CLK3, .... and so on. And there you are !! A 4 bit binary counter Hi Rohit, This way we will get asynchronous counter. Is it possible to make synchronous one using dff alone?