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Audio Sigma Delta Dac

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21 Threads found on edaboard.com: Audio Sigma Delta Dac
I presume you understand that most of the filtering of this delta-sigma dac is done in the digital domain by an oversdampling digital filter. According to datasheet, I would assume that the output filter is not required because the dac already includes an analog output filter to remove sampling residuals. There's no (...)
i have similar problem .. i am using pic32mz micro controller and uda1334 dac. (both supports i2s) i have shifted my data with 0x7fff. but output shows no change.. currently i am feeding a saw tooth wave to device.. i can see digital pins are toggling on CRO. but no output
Hi All I am having a problem with a dac and I need a little help. I am attempting to stream audio from an iPhone via Bluetooth. I have an FPGA connected to the Bluetooth chip via an I2S interface, so as the audio comes in I am passing it along to the delta sigma dac and from there of (...)
Hi everyone, I'm going to realize an audio player with a PIC32, using PWM as a dac for audio output. I have not write any code yet, because I want to understand deeply the theory behind it. I stored a .WAV file, 44.1 Khz sample rate, 16 bit, in a SD card, in a previous part of code. Now i want to reproduce this audio (...)
In my device I need pretty fast dacs - ideally 16 bit, with less than 3.5 us settling time, SPI interface. There are plenty of them, but all of them are quite expensive (for mass production; and I need 8 of them on a single board). Then I noticed that there are a lot of "audio" dacs with standard resolution of 24bit or better, and sampling (...)
Hello everyone......... I am working on sigma delta Modulator For audio Range of 0 to 20KHz..... I designed the two stage class A/AB amplifier, internal positive feedback hysteresis comparator and 1 bit dac.... My supply voltages are 0 to 1.8V in 180nm of technology in CADENCE.... But for both amplifier and (...)
I just want to design a audio dac, architecture: sigma delta dac + class D driver I don't know the equivalent model of the headphone if no LC filter is used on pcb,is class D still work? i mean if we can hear the voice normally?:-o
1 bit ( it is called sigma-delta encoding for ADC) OTherwise dac's use R/2R switches to convert D 2 A. The other method is logarithmic like A law using in American Telephony or ? Law for the ROTW but that is based on high dynamic range companding with 7 or 8 bits. Compression on short bursts works poorly since you need a library of sounds (...)
Hi, This is my first post on here, wasn't sure if this was better suited in this forum or the FPGA forum, please move if appropriate. I'm in the progress of developing a S/PDIF input delta sigma audio dac on a Spartan 3E 500k FPGA. I have completed the S/PDIF receiver and works well with a very simple 8-bit first order (...)
Hello, I have to build a mp3 player... This is what I think is cost effective... 1. Burn the music files in SD card 2. Use PIC(16 series probably) to fetch the files through SPI 3. Connect audio amplifier IC to the PIC 4. Send the music file to the audio amplifier. 5. Connect two small speakers to amplifier. Please let me know
Dear All : No I work in delta-sigma dac design , I need a good opamp (single-end ) for the low pass filter design, I read some paper , It need High DC gain about 90dB , Unit-Gain Bw is large 75MHz, The Noise is about 2~3 uVrms (20~20KHz). Does anyone work in this filed, And good OP Structure can share it , Thanks
delta-sigma converter may be the best solution for audio dac.
Dear All : I will design above 100db dac for audio codec , Does anyone have good document ?
I will try to answer some: 1. sigma delta is suitable for small bandwidth and high resolution applications (typical for audio). It can be used for dc. There are techniques used to overcome the idle tone problem + higher order loops suffer less from this problem. 2. Latency is a function of the resolution needed. You can roughly (very (...)
160 MHz to 1.25 MHz is a factor of 128 (7 bits). Why do you have only 4 bits? audio outputs commonly use delta-sigma dac techniques (not simple PWM) to get high amplitude resolution from a modest clock rate. Here's an introduction:
I will rather say 16 bit SAR ADC is doable provided the MSPS is not very high ! Go for Time Interleaved SAR ADCs !! 2 SAR ADCs 8 bit each working in time-interleaved fashion will do ur job !! Added after 1 minutes: If its audio, its very possible !!
I meet a confuse question. When I design the filter, how to decide phase margin. For example, if the passband is 24k (that main are used in audio), becasue of the no-ideal tansform function, the phase will shift from 0 after the low pass filter. So what is the spec for this design, is it 20 or 40 degree shift. Which number is reasonable for aud
hi which dac architecture is suitable for audio applications like mp3 players / cd players etc. thanks
There is always difference between theoretical & pratical limit in analog IC design. Could someone give me some figure or estimation about the degradation of sigma delta ADC/dac from the ideal (theoretical) SNR calculation using different architecture as shown below? I found the SNR estimation in text book as: [Modulator (MOD) , (...)
SMV coder for 3GPP2. Select mode vocoder. Developed by Conexcent and other companies. Mpeg4 audio, which includes a 2 kbps low bit rate speech coding developed by Sony. It uses hormonic coders for voiced speech and CELP for unvoiced speech.