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49 Threads found on edaboard.com: Bandgap Layout
Do the dkit mismatch models work correctly when resistors which should be matched are not in common-centroid layout? For example, a coleague designed a bandgap reference, and its design has three resistors that should be matched, but when he draw the layout, he put the three resistors in thi way. R1 R2 R3 (R1, R2 and R3 are made up of (...)
In band gap circuits, in layout if we have bjt 1:8 or 2:16 ratio the matching is done in such a way by keeping one bjt in centre and the remaining 8 surrounds the centre one(3X3) format.Can any explain the reason behind these matching concept?? thanks in advance
Hi Guys, I have a concern on the bandgap design. I have covered the process/voltage/temperature + montecarlo simulations on both the pre layout and post layout simulations, and the result are in the expected range with typically ~1.2V of the bandgap output voltage. The montecarlo simulations were performed around 1000 (...)
Hai everyone,this is Pallavi.I am going to complete my training in custom layout(industrial oriented) training by this August with the following designs: 1.Standard cells-INV,AND,NAND,NOR,XOR,MUX,OAI,DFF 2.Analog circuits-LevelShifter,Op-amp,bandgap,DAC,PLL can any of you please refer me to have a better careerpath in my life. Hoping you will..
Hi, I am currently debuging the bandgap and LDOs peaking at 3V power supply problem; please refer to the attachment 70540 the norminal VDD is 3.3V, and I look at the schematic, simulation results shows OK, no much variation with power supply change, also the phase margin of LDO is 53 degree, also layout should be ok too
Hi, currently I'm designing a bandgap voltage reference. I need some recommendations on the software(s) that able to draw the schematic and simulate it for the results, at the same draw the layout. I have Mentor Graphics in campus but unfortunately, it's closed on weekend. I have to work from home now. I need a solution (Freeware) ASAP! I have
Hello everyone, I am currently designing a bandgap reference (BGR) circuit in IBM cms9flp. Using Assura for LVS the circuit is shown to be correct (layout schematic match, and no extraction problems) When I use Calibre the result is Correct again, there are no extraction problems, BUT there is an ERC error. The description of the e
I am using cmos9flp IBM that offers vpnp as forward bias diodes for bandgap design. In the LVS I get an error showing that C is connected to sub! instead of VEE. Has anyone any idea how to overcome this error? D.
I have to design a buffer which buffers 0.6V voltage (which is coming from bandgap ...) to some other block. Any noise/ sudden variation at the output should not affect the input of the buffer. what do I need to consider in my design (not layout), to make sure that this noise doesnt reflect at the input? Thanks
Hello! I designed bandgap voltage reference. In attachement is PSRR jpeg. Tell me please: does this PSRR normal or bad? Exactly what about 0 dB crossing? If it's very bad how correct this without topology and layout change? Maybe capacitance at the Vref node? yes, it is quite normal graph for PSRR. but maybe you can
Hello everybody, I am new to design of BGR, The question is that the selection of diode ration(1:n). Commonly every one prefer 1:8 to achieve good common centroid configuration in layout. But is there any ratio which is leass than 8? Thanks inadvance. bharat
Can anyone elaborate the detailed points to review a bandgap layout.
There will be a layout for a transistor in the PDK for the process and you MUST use that. Then you use multiple transistors for the bandgap. You DON'T do what you have drawn. What is the process? Also 10:1 is a strange ratio - difficult to get a good layout. Powers of 2 are better. 8:1 is good - a 3x3 matrix with the single one in the (...)
How to check the operating point of the start up circuit of the bandgap reference is turn off after the whole circuit is working? (when i ramp my input from 0 to 5V) You can use the writefinal option. See this thread . ... can anyone give me so
A lateral BJT with base width under a micron, is probably only going to be geometry-repeatable when drawn as a self-aligned structure. That means a MOS gate over the base region, a lightly doped (rather than mid-doped) base and a high pinched base resistance. Possibly suitable for a very low bandgap current, but with the gate over base it w
hi all im designing a bandgap reference with two serial bipolars but im stuck at layout. i need to know a technique for implimenting this circuit , i red that diode ratio must be 8:1 but i dont know the reason. if anyone can help me with designing layout for: a)the cascoded current mirror(which consist of pmos) b)the opamp c)diode (...)
Hi, Can anyone comment on the minimum spacing requirement between bandgap reference module layout and DCDC regulators(w.r.t.switching node)module layout in 65um technology to minimize the transmission of noise generated by DCDC ?PowerFETS inside DCDC are well surrounded by double guard is inside a power management IP used in a SoC .
Hi,everybody! I have some problems about bandgap circuit design here. Those are below: 1、The ration of the two transistor area is usually 8 ,not 4 ,16 ,why? 2、Why is the temperature coefficient of Vbe -1.5mv/k to -2.3mv/k?; what is it related to? 3、what type of BJT is ususlly used ?why? 4、What typ
Hi! I design LVDS transmitter. Power supply is 2.5, transistors with thick oxide. layout is standart: 2 nmos switch, 2 pmos switch, bandgap, bandgap based current reference and CMFB. In DC this work good: Vos stable. Vol Voh also. But when modeling transient process there are distortion at the moment of switching. Vos, Voh, Vol go up (...)
start from read book, then with simple case, just for bandgap circuit, opamp etal.