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Hi I am working to interface EEPROM and 89c2051.I am started with counter program (0-9)values display in bcd 7 segment. When I pressed button P3^5 ,R/W process works well.After that in my For loop it wont Write Data in EEPROM.I dont know where I am going wrong?I anyone know the reason share with me.Here I attached my code Simulation
Hi, You could use programmable logic as single chip solution. CPLD (Or older GAL, PAL...) You could use a microcontroller as single chip solution. You could use two HC390. You coud use ICM7217 as 4 digit decimal counter with multiplexed bcd outputs (+ 7 segment LED display controller) ... Klaus
Who know how 2 make bcd counter to 7segment led using 825 ORG 0000H PORTA: EQU 80H PORTB: EQU 81H PORTC: EQU 82H CTRL: EQU 83H MVI A, 10001001B ; Control word setting where Port A AND B = O/P and Port C= I/P. OUT 83H ; Send control word to control register. MVI A,00111111B OUT PORTA
Do we need to assume ourselves that you have used 555 timer ic in astable mode and you have used bcd counter and the 7 segment display to display the timervalue?
You know google usually works pretty good when searching for a simple query like this "bcd counter vhdl code"...the first returned link is: it uses t
Start with making a state Diagram of all inputs and outputs ( including transient switch contact states) Your inputs are 2 switches Normally Open (NO) connected to ground or Vcc with SIP resistors or discrete R's to the other polarity. Your Outputs are either 7 segments for Common Cathode LED you specified or using a bcd to 7Seg chip.. Your homew
Hai all i need a program for control 8051 to bcd 4511 to count down the timer for example port 1 has 8 pins if a select p2^7 means eight minutes want to decrement to zero include seconds to. I need to know how should i program for interface using single ic 4511 to access four segment led
i need bcd to 7 segment with should count from zero to 3 plz help
Hi all, am desining a 7-segment LED clock using 4017 as the couter and 4511 as bcd 7-segment driver. The clock is working just fine with the british method of 24:00 hours but i want it to count 12:00 hours and jump back to 01:00 instead of 24:00. No microcontrollers. I will appreciate if any one could help me out.
I am trying to set up a a 4-bit binary counter to rest at count ten. Since I didn't have LS390' I had to create a condition rest clock made from an AND gate chip. First I used one gate to get triggered when Qc and Qa where active. However when I do this it only
It sounds as though you are looking for a 'count to N and halt'. A 4017 (1-through-10 sequencer) might do the job. You can tap off any or all of the 10 output pins. Skip one or two pins, when you need a delay. An alternate IC is the 4028 (bcd to decimal decoder, or 'select 1 of 10'). It would need input from a counter circuit to make it work.
hi all can someone help me in this question We would like to design a 2-decade up/down bcd counter in HDL language using behavioral description. Since the counter is a 2-decade one, it is thus able to count from 00 to 99 and then back to 00. The counter has the following input control signals: 1. Load signal to (...)
We would like to design a 2-decade up/down bcd counter in HDL language using behavioral description. Since the counter is a 2-decade one, it is thus able to count from 00 to 99 and then back to 00. i need the code?
I posted a 3-digit bcd counter code in this it's for a Spartan-3e kit, it might help you in coding. And try commenting your code as it helps others analyze it. Regards...
Below is the code for a 3-digit bcd-counter (Binary Coded Decimal) I implemented while studying Verilog. You have to change the compare values (I commented on the code) to make it count like a clock (i.e. up to 60 instead of 100) and you can also add more digits for a full scale clock. You can access the driver for the lcd here: [URL="www.e
I am trying to implement the Intel 8253 PTI , i have written the code for the Binary counter and the bcd counter that i need to instantiate in the Main Code for 8253, but now i am facing some problem with the modes , as for every mode the Gate Input acts differently and effects the count in a different manner , so i cant make so many (...)
hi am using a MC14520B bcd IC, which according to its waveform diagram, counts up to 0-15 decimal. I have built a test box, 555 timer generating 1hz clock , into bcd IC, then out to ADG406 multiplexer test box is used to check 14 way multicore cable, each output from mux is connected to one end of cable, molex connector, then other end i
hi all i need vhdl code for 0-99 bcd counter 7-seg display code Changed by pressing the Button tanx
I have created a binary to seven segment verilog module which works in isolation when using switched for the input however I want to instantiate this from another module which counts, using the binary to seven segment module to display the count. The two modules are as follows. module bcdtoSevenSegment(out, bcd); output out; in
I am trying to write the VHDL code for a Timing Genarator Chip : in the VHDL code i have to incorporate a code for the 16 Bit bcd(Binary Coded Decimal) counter i.e. 4 Decades , i tried a lot but unable to figure it out how to get it working... as the 16 bit bcd counter can count from 0 to 9999 ,for the first 9 clock pulses (...)
>@ Mister_rf , Allow me to explain my concern on the Opto Design. Short path = no issue. Long path = some concerns Threshold of detection is dependant on; gain of photo-transistor (huge variance and aging effect) value of emitter resistor noise of stray light affecting shadow levels strength of stray reflections
Hi, I am trying to simulate a bcd counter in Hspice, as you know bcd counters are consisted of flip-flops such as JK-FF. In my circuit there are four JK-FFs, the flip-flop subckt is working properly, I mean when I simulate a single JKFF individually in a netlist it works properly, but when I connect the JKFFs together the (...)
hi all,,,,,,,,i made a 640x480 VGA controller in VHDL using Spartan-3. AND, i could display characters too. now, i'm trying to display a digital clock on screen. i tried to make bcd counter and address variables to the characters , but it didn't work. the question is, how i can combine the vga controller code and clock together , and addres
hi friends, i think we can change bcd to 7segment display by ic 7447. do know any ic that can change binary to 7seg? even if 2 segments are acceptable! thanks
Hi I have a vhdl code counter that counts in binary from 6 to 88 then it rolls over to count down from 88 to 6. Now i want to do the same counter but instead of counting in binary i need it to count in bcd. can i show the count values in quartus in bcd? if not please any help how can i do that? thank u in advance.
Hi Guys I have designed a bcd-counter that gets displayed on 2x 7 segment displays. Each display counts 9 and resets, i.e the least significant display starts off at 0 and when it reaches 9,it resets to 0 and it increments the most significant display to a one and so on. But the counting sequence of the least significant is not counting sequenti
The HC160 & HC161 are virtually identical - the HC160 is a bcd rather than binary counter so the circuit should be fine. I have simulated it and it looks ok. The parallel load is 5 in my example so the counter counts 11 pulses (= 16 - 5). Keith.
Actually, a really cheap, poorly made, pushbutton connected directly to the clock input of a decade counter can also produce a random count. No need for a 555 timer or other clock circuitry. One case where switch bounce is a good thing! Then a bcd to decimal decoder can be used to drive only one LED at a time. This would work for up to 10 LEDs if a
Hi all, I am designing a four digit 7 segment display just using IC 74LS90 decade counter and 74LS47 bcd to 7 segment driver. My question is how to link the 74LS90 decade counter together so that the four 7 segment display will show me the result?
I have to design bcd counter with JK Flip Flops which should have Asynchronous Parallel load (Active high) Synchronous Reset (Active Low) What we mean by both these terms
Hello guys, Does anyone know how to design 16-bit up counter using verilog HDL? from the binary output produced, it need to be converted into bcd. Then the decimal number will be display at 7-segment. Does anyone know the step/flow should be done for this experiment?
its my first basic code which is completely working fine... Its specially for all those beginners who dont know how to divide (decrease) the clock speed... u can also check out my video => codes are as follows: counter code: library ieee; use ieee.std_logic_1164.all; use ieee.numer
hey friends.. i am creating a digital timer with bcd counter but the problem is if the power is turned off its it starts again but i have to make like this if the power is switch off it should paused and start from the paused value when the power switch on again.. help me guys thanks ..:D
I have searched the forum but couldn't find what i wanted exactly.. Say i have an output from an 8-bit binary counter "95" .. I want to display it on 7-segment displays on a spartan 3E FPGA board.. What is the solution of this problem even if i got the bcd conversion, how can I display it on 7-segments? Thanks for your concern..
you can create a 2 digit bcd counter by using two 4 bit counters and some logic gates.The main idea is that when the count in the first(LSB) counter reaches the value "1001"( 9 in decimal) it is reset to zero and the second(MSB) counter is incremented by '1'. I am not sure about why you need a 4:1 MUX for (...)
i need to do a project in verilog> design an 8-bit bcd counter using 2 74163 counters and multiplexer 4:1 TABLE OF CONTENTS 1. Project theme -design an 8-bit bcd counter using two 74163 counters and multiplexer 4:1 2. Theoretical approach 3. Structural description of the (...)
Hi Convert the data on port B to ASCII or to bcd and save it in a RAM array Indexed by a counter unsigned char Array; unsigned char Index = 0 ; Array =Port_B_Data ... All the best Bobi The microcontroller specialist
I need to modify an older counter where 74F190 chip died. Is there any chance to make a substitution with 74LVC (maybe 74LVC109) chips that can count up to 200MHz. Needed is only decade UP counting and reset to 0.
You need a three bit bcd counter. A nice article is to be found shold also read about flipflops to be able to give an answer to the
i need to do a 2 digit bcd counter testbench verilog ,here i attached the verilog but i dunno correct a not Where is the attachment Nandhu
Hi, I need to implement a simple VHDL frequency counter for a school project. Must be 4 multiplexed digits. (the FPGA as few macrocells). I know how to implement the counter and the bcd to seven segment. is the multiplexing and puting things togheter that i need help. Can anyone point me to an example? Must be very simple. Thank (...)
Here is verilog code for 8 bit bcd counter module bcd_counter (clk, rst_n, count); input clk, rst_n; output count; reg count; always @(posedge clk or negedge rst_n) if (!rst_n) count <= 8'h00; else if (count == 9) begin count <= 0; if (count == 9)
Hello to all, I?m newbie in VHDL programming on FPGA. I need help from all of you out there. Right now I try to write a code for 2-digit bcd down counter, LCD display message and synchronization between both of them. For 2-digit bcd down counter, here?s my code library IEEE; use IEEE.std_logic_1164.all; use (...)
Are you using SystemVerilog? That module won't compile in Verilog because this statement can't go inside an 'always' block: reg hour1,min1,sec1; I moved it up a few lines, and now it compiles fine (I'm using ModelSim in Verilog mode). It appears to simulate fine too. It's a 24-hour bcd clock. What malfunction do you s
I have ton ot good examples of bcd or decade counters but NONE have a "real" counter which can be loaded with arbitrary value just like the one depicted on the pix, which is a genetic SN74LS168 up/down ripple bcd counter with load? Building it out of D flip-flops and ton of gates as the function diagram (...)
can some one pls help me to design the prob with orcad or Multisim7/8 ? I know we need a : decoder/ encoder/ JK FF/ counter/ 7 segments and bcd to 7 segments driver but I can't get it work. see attachment
Here is verilog code for 16 bit bcd up counter translate this to VHDL! Hope this helps! module bcd_count ( // Outputs count, // Inputs clk, reset_n ); input clk, reset_n; output count; reg count; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin count <=
Here it goes!! For this simple counter No need to have Statemachine! module bcd_count(clk, reset, ce, count); input clk, reset; input ce; // count enable output count; // two digit bcd counter reg count; always @(posedge clk or posedge reset) begin if (reset) begin count <= (...)
This seems to be ur homework!! The problem is clear and simple you have to write verilog code for the digital clock! Start with the counters hours => 00 to 23 bcd counter we need two such counters one for clock and one for alarm setting minutes => (...)
bcd caunter for 8051 microcontroller.