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1000 Threads found on edaboard.com: Ber Performance
Hello, I am trying to perform post implementation timing simulation of attached circuit in vivado 2016.2(). I am able to do behavioral simulation with all the objects visible (pls refer attached eda_bs). But when i start post implementation timing simulation, i am unable to see d listed in objects tab(pls refer attached eda_pits). Anyone
What are best designs worth trying? Some starting point. Maybe few insights from someone who tried to build such joint and any interesting materials (patent/video/etc.). Interested in leg/arm joint that achieves performance close to SpotMini. As I understand high torque fast motor is a problem, b
I want to design in practical a ring resonator on substrate like rogers rt duroid 5880. With those rings, I want to use some passive/active components as well in order to improve performance. This would be helpful if someone guide me how to do this in Ansys HFSS. I can design ring embedded on substrate in Ansys, but component like resistors, capaci
Hello, I want to design in practical a ring resonator on substrate like rogers rt duroid 5880. With those rings, I want to use some passive/active components as well in order to improve performance. This would be helpful if someone guide me how to do this in Ansys HFSS. I can design ring embedded on substrate in Ansys, but component like resisto
I have no doubt that adding a dedicated relay to supply current for starter solenoid (Which suggested is also a relay) will alleviate the pain experienced by factory ignition switch internals, and it may have a positive influence on cranking speed but that waits to be tested. You are confusing the current paths. Cranking speed is de
Question: What are the layout guidelines that will allow me to minimize the Y1 mil & Y2 mil sizes (see attached picture) such that the below 10MHz OCXO frequency stability will not have a performance degradation? Do I have to place the GND between the OCXO out to Vc etc. or maybe I can remove it? What is the required distance between OCXO out and
Hi Is there any procedure to theoretically/analytically find out how the optimum impedance values obtained by load-pull change as the frequency increases? I have seen in most cases impedance moves on the smith chart in anti-clock wise direction as the frequency increases. Is this true in every case ans why?. Thanks
Hello all , I' m working in design of harvesting energy circuit and i would like to knew the definition of efficiency as parameters of performance ?! Regards!
Hello, I am going to create a 10Ghz oscillator with frequency multiplier. I curious to know what happens if I use two back to back 10X multipliers and four multipliers (2X,5X,2X,5X). what is the best consideration for choosing frequency multiplier?
Hello, If I "migrate" to OpeCL language for programming FPGA, will be any difference in speed running the "same" algorithm? I mean if I have an algorithm built in VHDL for Spartan 3E and the same algorithm implemented in OpenCL. Will I see any difference in speed? Is there any other difference practically between OpenCL and VHDL? Thank you
New v0.5.3 Tk/Tcl Support Find IPCore instances from IPCore tree context menu SBAlibrary as external executable Template autocomplete support in templates.ini (example: write li
153641 I need a high performance integrator. And I want to check 'Stability of the integrator block'. So I designed it like the figure, and assigned it as the STB instance of SPECTRE at the place labeled VAC and simulated it. Loop gain and phase margin are shown in the figure. The area marked in red has a gain great
Many designs to be found on the internet have performance problems and/or are overly complicated. A lot have poor loop compensation or none at all, covered up by an oversized output capacitor. This design actually evolved from one of these dysfunctional designs. It is genuinely stable and needs one control rail. There is a small current flow
Many designs to be found on the internet have performance problems and/or are overly complicated. A lot have poor loop compensation or none at all, covered up by an oversized output capacitor. This design actually evolved from one of these dysfunctional designs. It is genuinely stable and needs one control rail. There is a small current flow
153672 I'm trying to figure out how does this radar system works. Transmit Gunn diode is driven by mixing oscillator logic 3% duty cycle pulse with delta f logic, triggered on the falling edge of oscillator logic by a circuit with two MOSFETs, several resistors and one MOSFET driver to push/
Hi I have a passive backplane with usb connectors intended for usb 3.0. What is the required eye size of input, output to the backplane if it should be compliant to USB3.0 (not a usb-if member)? Is it correct to only simulate the backplane itself or must s-parameters be used for reference host, device together with backplane to measure the eye
Dear friends, I have different PMOS matched transistors matched in different groups but all they have the same bulk potential (bulk connected to the VDD), if these groups are near to each other is it better to attache both of the well and makes the groups share the same well as much as possible? or may separate wells give better performance ?
hello everyone, I?m a bit stuck in the concept of load pull? I?m using ADS to model and tune a amplifier, my questions are: (regardless of stability) 1- by loadpull, we simulate the effect of different loads on the performance of the system. Imagine I picked the load ZL which leads the amp to have the best performance. As I assu
Hello everyone. I am building an audio amplifier using transistors, based on a circuit taken from "Art of Electronics". In the book, the circuit is presented without load resistance, and I understand quite well how the circuit works in general. In my case, I need to have an 8 Ohm resistor at the output, and I can notice that the output voltage i
Broadband impedance matching is quite different from narrow-band matching. There is a theoretic bound for returnloss if the matching network must be lossless. You can not obtain better result than the bound with finite number of lossless components. Usually people solve the problem from different approach: 1. Use numerical optimization to search