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Here is Hint. Use real type. If you want to output real on ports use $realtobits and $bitstoreal functions. Hope this hint helps
The Verilog "real" type uses IEEE 754 double-precision (64-bit) floating point format, and that contains 2's compliment exponent and mantissa. You can use $realtobits() and $bitstoreal() to convert to/from a 64-bit vector.
Is there any way to pass real-values thru input/output ports in verilog-xl? Not in Verilog, there are 2 system tasks: $bitstoreal, $realtobits that will convert real <-> 64 bit reg - that should help you here. HTH Ajeetha -- Interested in expert PSL/SVA training in Bangalore? Visit www.nove