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I'm trying to design a self contained DC bus power supply. Specifically it's for a 400v 2200w AC servo drive. Trying to get this all down on 1 PCB for simplicity. I've been using this drive for some time with just 240v mains rectified to 340vDC and some filter caps. The inrush current on charging the caps from flat is rather large, Which for a whil
my current starved vco oscillations are dying out after some nanosecond. what could be the possible reasons? and how to rectify it?
I added a new excitaion signal by importing ASCII file BUt the cst gives this below and suddenly aborts : The current settings will lead to an extremely long simulation time. You may improve the simulation speed by: 1. checking the frequency range and units settings 2. reducing the simulation duration 3. checking the mesh to avoid (...)
Hello, Is it possible to do circuit HFSS cosimulation when I am planning to use floquet port for unit cell of metamaterial structure part simulation. Thanks
Hi guys, I'm trying to design a transimpedance amplifier for optical receiver, based on this acrticle: the requirements: -VDDA=1.8V -Cload = 200fF (the output of the amp loaded by 200fF) -the total gain At=Vout/Ipd = 3000, (Ipd is the current source on the left on the schematic) -BW>2
Hi, Recently, I got this BLE v5 dongle , I plugged it to an ubuntu machine and started to check it using these commands $ sudo hciconfig -a No output $ sudo hcitool dev Devices: $ sudo hcitool lescan Could not open device: No such device But linux c
Hey all, I am using Verdi for simulation of RTL. We have lot of assertions in design and I would like to know if an assertion is fired in a simulation or not. There is a assertion debug mode which should list out all the assertions, however, I am not seeing any information if it is passing, failing, checked, or not at all fired. Is there some ki
hii, why requred to simulate atpg pattern in vcs but Synopsys Tetramax tool also option of run_simulation? Thanks,
Can the momentum simulation results be better than the simulation result of the schematic?
Hello, attached is the transient pic of the fully differential amplifier I have designed, if you look to the vo+ and vo- you will see the sparks on it, however the differential coltage is clear due to the subtraction, my question, should I be concirned about the individual outputs or only have to look to the differential output (Vo_diff)
Hello, I am trying to design a split ring resonator and extract the material properties. But before doing that I thought it's a good check what my simulation gives me for known material. I selected Teflon as my material and design floquet port in order to extract the material properties like permitivity over the frequency range. However, I am n
Hi All, I'm wondering about which Monte Carlo setup will accurately represents statistical distribution in silicon on mass production. There are 2 cases that I'm considering: Case-1: Global Corner + Local MC In this case I vary the Corner manually (ie. Typ, Fast, Slow, FS, SF) and run Local MC with each of them Case-2: G
I would like to design a dc booster for a solar system. System consists of 6x 265Wp panels in series, which equals roughly 1600Watts, 200V, 9 Amps. I need to boost the voltage up to 350V to feed into a VFD which in turn drives a 0.75kW motor. Is this possible? Where should I start? Thanks
i have downloaded 32nm finfet ptm model file.after extracting files i got all pm files.could you please tell me how to get sp file
Hello, I see that slotted waveguide antennas are usually built from elements with diagonal offset (as shown in attached figure). The longitudinal offset is understood to me (phase difference), however the horizontal offset is not clear. If the waveguide is excited by TE 10 fundamental mode, the E field keeps his sign along X axis. Can you
Hi guys, I designed a PLL, and I'm not getting to a locking state yet. I'm trying to debug the problem by observing the behavior of different signals. It seems that I'm getting only Up Pulses and the behavior is periodic. here is one that simulation that shows the periodic behavior of Up pulses: 157210 [ATT
Hi in CST 2019 "Equilibrate mesh ratio" seems does't work as soon as I apply changes but I have to run "History list update" to see the effects before simulation, same issue I found on Local Mesh Is anything changed from CST 2014 ? thanks
The phase margin is 72 degree when the gain is 0dB. However, the phase margin is close to 0 before the frequency reaches the unity-gain bandwidth. Is the op-amp stable? Why? Thank you. 157193
I have downloaded BSIM4 from Berkeley website. All the source codes are in C language. Do you know how to start running this source code? How can i use it? Thanks
Can simulator like ncverilog simulates the metastability behavior of CDC circuits? How to do simulations with metastability models (RTL and gate-level)?